mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
5274be0191
because not all emulators get the ram size registers right, or so we hear. This northbridge is still incomplete. We are not just copying the v2 one, as we are trying to undo the various hacks that crept in over the years, due to limitations in the v2 device model. Just look at the i440bx in v2 and you can see what I mean. We are working to find a better way to get the job done than those hacks. They are just too confusing for people to follow. add an include for the northbridge makefile into the qemu Makefile. Re-order the includes in arch/x86/Makefile so we can pick up .o files from other places. Add a STAGE2_CHIPSET_OBJ for objects defined in those makefiles included in mainboard. Current issues: the enable_dev function for the i440bx is not getting called. Enable_dev should be renamed to phase3_setup or something that actually means something. The name as it is is totally useless. Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@138 f3766cd6-281f-0410-b1cd-43a5c92072e9
34 lines
No EOL
571 B
Text
34 lines
No EOL
571 B
Text
/{
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config="mainboard,emulation,qemu-i386";
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cpus {
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emulation,qemu-i386@0{
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enabled;
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on_mainboard;
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device_type = "cpu";
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name = "emulation,qemu-i386";
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pcidomain = "0";
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/* the I/O stuff */
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northbridge,intel,440bx{
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config="northbridge,intel,i440bxemulation";
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pcipath = "0,0";
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southbridge,intel,piix4{
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};
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};
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};
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};
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};
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%%
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struct mainboard_emulation_qemu_i386_config root = {
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.nothing = 1,
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};
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struct northbridge_intel_i440bx_config northbridge_intel_440bx = {
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.ramsize = CONFIG_NORTHBRIDGE_INTEL_I440BXEMULATION_RAMSIZE,
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}; |