mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
51676b14e8
This reverts commit 042c1461fb.
It turned out that sending IPIs via broadcast doesn't work on
Sandybridge. We tried to come up with a solution, but didn't
found any so far. So revert the code for now until we have
a working solution.
Change-Id: I7dd1cba5a4c1e4b0af366b20e8263b1f6f4b9714
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/1381
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
62 lines
1.1 KiB
ArmAsm
62 lines
1.1 KiB
ArmAsm
#include <cpu/x86/mtrr.h>
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#include <cpu/x86/lapic_def.h>
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.text
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.globl _secondary_start, _secondary_start_end
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.balign 4096
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_secondary_start:
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.code16
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cli
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xorl %eax, %eax
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movl %eax, %cr3 /* Invalidate TLB*/
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/* On hyper threaded cpus, invalidating the cache here is
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* very very bad. Don't.
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*/
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/* setup the data segment */
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movw %cs, %ax
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movw %ax, %ds
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data32 lgdt gdtaddr - _secondary_start
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movl %cr0, %eax
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andl $0x7FFAFFD1, %eax /* PG,AM,WP,NE,TS,EM,MP = 0 */
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orl $0x60000001, %eax /* CD, NW, PE = 1 */
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movl %eax, %cr0
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ljmpl $0x10, $__ap_protected_start
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gdtaddr:
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.word gdt_limit /* the table limit */
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.long gdt /* we know the offset */
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_secondary_start_end:
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ap_protected_start:
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.code32
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lgdt gdtaddr
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ljmpl $0x10, $__ap_protected_start
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__ap_protected_start:
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movw $0x18, %ax
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movw %ax, %ds
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movw %ax, %es
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movw %ax, %ss
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movw %ax, %fs
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movw %ax, %gs
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/* Load the Interrupt descriptor table */
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lidt idtarg
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/* Set the stack pointer, and flag that we are done */
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xorl %eax, %eax
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movl secondary_stack, %esp
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movl %eax, secondary_stack
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call secondary_cpu_init
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1: hlt
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jmp 1b
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.code32
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