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https://github.com/fail0verflow/switch-coreboot.git
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51067116eb
BRANCH=none BUG=chrome-os-partner:31936 TEST=build and test on ryu Change-Id: I2bd1b2c2b1bfe75702a12129ca57b3afa6542575 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 6aac5ecb014ab213f465b9aa78f587994c6b3624 Original-Change-Id: I64f2df49a258b4dd024305a9757704a823265e99 Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/229911 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9516 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
49 lines
1.4 KiB
Text
49 lines
1.4 KiB
Text
##
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## This file is part of the coreboot project.
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##
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## Copyright 2014 Google Inc.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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chip soc/nvidia/tegra132
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register "spintable_addr" = "0x80000008"
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device cpu_cluster 0 on
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device cpu 0 on end
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device cpu 1 on end
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end
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register "display_controller" = "TEGRA_ARM_DISPLAYA"
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register "xres" = "2560"
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register "yres" = "1800"
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# bits per pixel and color depth
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register "framebuffer_bits_per_pixel" = "32"
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register "color_depth" = "12"
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register "href_to_sync" = "1"
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register "hfront_porch" = "80"
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register "hsync_width" = "80"
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register "hback_porch" = "80"
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register "vref_to_sync" = "1"
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register "vfront_porch" = "4"
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register "vsync_width" = "4"
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register "vback_porch" = "4"
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register "refresh" = "60"
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# kernel driver
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register "pixel_clock" = "301620000"
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end
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