mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
505414a6cf
Use of uma_resource() in AMD northbridge code created a memory resource marked as reserved. Such resources are removed from system memory in write_coreboot_table(). Change-Id: Ib5e49e851d6622d8ece9d6d612e245b3962b9167 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1233 Tested-by: build bot (Jenkins) Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
95 lines
2.8 KiB
C
95 lines
2.8 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <arch/io.h>
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#include <boot/tables.h>
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#include <cpu/x86/msr.h>
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#include <cpu/amd/mtrr.h>
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#include <device/pci_def.h>
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#include "SBPLATFORM.h" /* Platfrom Specific Definitions */
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#include "chip.h"
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void set_pcie_reset(void);
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void set_pcie_dereset(void);
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/**
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* TODO
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* SB CIMx callback
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*/
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void set_pcie_reset(void)
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{
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}
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/**
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* TODO
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* mainboard specific SB CIMx callback
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*/
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void set_pcie_dereset(void)
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{
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}
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/**
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* Southstation using SB GPIO 17/18 to control the Red/Green LED
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* These two LEDs can be used to show the OS booting status.
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*/
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static void southstation_led_init(void)
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{
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#define GPIO_FUNCTION 2 //GPIO function
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#define SB_GPIO_REG17 17 //Red Light
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#define SB_GPIO_REG18 18 //Green Light
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/* multi-function pins switch to GPIO0-35 */
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RWMEM(ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEA, AccWidthUint8, ~BIT0, 1);
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/* select IOMux to function2, corresponds to GPIO */
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RWMEM(ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG17, AccWidthUint8, ~(BIT0 | BIT1), GPIO_FUNCTION);
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RWMEM(ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG18, AccWidthUint8, ~(BIT0 | BIT1), GPIO_FUNCTION);
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/* Lighting test */
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RWMEM(ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG17, AccWidthUint8, ~(0xFF), 0x08); //output high
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RWMEM(ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG18, AccWidthUint8, ~(0xFF), 0x08);
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mdelay(100);
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RWMEM(ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG17, AccWidthUint8, ~(0xFF), 0x48); //output low
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RWMEM(ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG18, AccWidthUint8, ~(0xFF), 0x48);
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}
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/*************************************************
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* enable the dedicated function in southstation board.
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*************************************************/
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static void southstation_enable(device_t dev)
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{
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printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
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setup_uma_memory();
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southstation_led_init();
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}
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int add_mainboard_resources(struct lb_memory *mem)
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{
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return 0;
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}
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struct chip_operations mainboard_ops = {
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CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER " Mainboard")
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.enable_dev = southstation_enable,
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};
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