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https://github.com/fail0verflow/switch-coreboot.git
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4bab6e79b0
Change-Id: I6ea9b9d2353c0d767c837e6d629b45f23b306f6e Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14599 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
56 lines
1.3 KiB
Text
56 lines
1.3 KiB
Text
#
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# This file is part of the coreboot project.
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#
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# Copyright (C) 2007-2010 coresystems GmbH
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; version 2 of the License.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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config SOC_INTEL_SCH
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bool
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select MMCONF_SUPPORT
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select LATE_CBMEM_INIT
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select INTEL_GMA_ACPI
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select SOUTHBRIDGE_INTEL_COMMON
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select HAVE_USBDEBUG
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select HAVE_HARD_RESET
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select HAVE_SMI_HANDLER
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if SOC_INTEL_SCH
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config VGA_BIOS_ID
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string
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default "8086,8108"
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config EHCI_BAR
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hex
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default 0xfef00000
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config HAVE_CMC
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bool "Add a CMC state machine binary"
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help
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Select this option to add a CMC state machine binary to
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the resulting coreboot image.
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Note: Without this binary coreboot will not work
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config CMC_FILE
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string "Intel CMC path and filename"
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depends on HAVE_CMC
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default "cmc.bin"
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help
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The path and filename of the file to use as CMC state machine
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binary.
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config HPET_MIN_TICKS
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hex
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default 0x80
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endif
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