mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
f28a44eb48
image, and fails: LAR build/coreboot.rom Bootblock coreboot.bootblock does not appear to be a bootblock. Error adding the bootblock to the LAR. make: *** [/home/rminnich/src/bios/coreboot-v3/build/coreboot.rom] Error 1 Next step is to get rid of all warnings that are not #warning. Then it is on to simnow. Anyone who wants to work on the warnings is most welcome to. DBE62 still builds with no problems. Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://coreboot.org/repository/coreboot-v3@808 f3766cd6-281f-0410-b1cd-43a5c92072e9
40 lines
1.4 KiB
Makefile
40 lines
1.4 KiB
Makefile
##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2007 coresystems GmbH
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## (Written by Stefan Reinauer <stepan@coresystems.de> for coresystems GmbH)
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; either version 2 of the License, or
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## (at your option) any later version.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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ifeq ($(CONFIG_SOUTHBRIDGE_AMD_AMD8111),y)
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STAGE2_CHIPSET_SRC += $(src)/southbridge/amd/amd8111/amd8111.c
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STAGE2_CHIPSET_SRC += \
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$(src)/southbridge/amd/amd8111/ac97.c \
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$(src)/southbridge/amd/amd8111/acpi.c \
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$(src)/southbridge/amd/amd8111/ide.c \
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$(src)/southbridge/amd/amd8111/lpc.c \
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$(src)/southbridge/amd/amd8111/nic.c \
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$(src)/southbridge/amd/amd8111/pci.c \
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$(src)/southbridge/amd/amd8111/smbus.c \
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$(src)/southbridge/amd/amd8111/usb.c \
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$(src)/southbridge/amd/amd8111/usb2.c
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STAGE0_CHIPSET_SRC +=
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endif
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