switch-coreboot/northbridge/intel
Uwe Hermann 7694517f9f Port r3747, r3732, r3733 from v2 to v3 (build-tested on v3):
src/northbridge/intel/i945/ich7.h:

Thanks to Uwe Hermann for spotting this typo.


src/southbridge/intel/i82801gx/i82801gx_lpc.c:

The enable_hpet() code in intel/i82801gx will not work with the
ICH7 southbridge (but it might work with ICH4/ICH5 or so).
The ICH7 needs a different init code. Drop the non-working code for now.


src/southbridge/intel/i82801gx/i82801gx.h:

Drop #defines for registers that are not existant on the ICH7.
Also, fix BIOS_CNTL, which is 0xdc on ICH7.
Build-tested with kontron/986lcd-m.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@1107 f3766cd6-281f-0410-b1cd-43a5c92072e9
2009-01-08 16:14:12 +00:00
..
i440bxemulation This patch should serve as a porting help for other northbridges for the new resource allocator. 2008-12-31 20:00:30 +00:00
i945 Port r3747, r3732, r3733 from v2 to v3 (build-tested on v3): 2009-01-08 16:14:12 +00:00