switch-coreboot/src
Ionela Voinescu 3fa1ad0d2c pistachio: add DDR3 initialization code
Initialization for the Winbond W631GG6KB part using Synopsys
DDR uMCTL and DDR Phy.

This code adds a separate function for DDR3 initialization
and moves all the necessary defines in a separate header file.

The programming procedure that is executed at power up to bring
up the uMCTL, PHY and memories into a state where reads and
writes to the memory can be performed is the following:

1. uPCTL (Universal DDR protocol controller) initialization
   The timining registers TOGCNT1U, TINIT, TOGCNT100N and TRSTH
   needed for driving the memory power-up sequence are programmed
   as a function of the internal timers clock frequency.
   Organization (memory chip specific) values are set
   (column/bank/row address width and number of ranks), together
   with other static values (latency, timing, power up configuration).
   All these values are static, provided by the datasheet,
   being determined by the memory type, size and frequency.
2. PHY initialization
   The PHY is programmed with datasheet provided values,
   specifying the initialization values for it to send to the
   external memory (timing parameters).
   Also, delay lines (DLL) and strength of drive pads are
   calibrated (based on external conditions: temperature,
   voltage, noise) and locked. After that, the PHY goes
   through a trainig process (also dependent on the
   current conditions at boot time) to establish precise
   timing configuration between the DDR clock and DQS (data strobe)
   and between DQS and DQ (data).
3. Memory power up
4. Switch from configuration state to access state.

It was tested on Pistachio bring up board where DDR was initialized
properly and ramstage executed correctly

Change-Id: I3bcbce2044327a22fce09b184d85ee11228a6b2b
Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Reviewed-on: http://review.coreboot.org/10529
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-12 20:19:42 +02:00
..
acpi acpi/sata: add generic sata ssdt port generator 2015-06-07 01:24:47 +02:00
arch lenovo: Hide SMBIOS config 2015-06-11 13:20:56 +02:00
console consoles: remove unused infrastructure 2015-05-26 19:02:54 +02:00
cpu model_2065x: Use common i945-ivy TSEG SMM init. 2015-06-10 05:34:01 +02:00
device resource: Refactor IORESOURCE flags use 2015-06-10 05:51:51 +02:00
drivers lenovo: Hide SMBIOS config 2015-06-11 13:20:56 +02:00
ec lenovo: Move pc_keyboard_init to h8 init. 2015-05-29 07:45:55 +02:00
include Clearly define printk log level use cases. 2015-06-11 20:18:49 +02:00
lib stage_cache: use cbmem init hooks 2015-06-09 22:06:40 +02:00
mainboard google/jecht: fix MAC address programming when VPD not present 2015-06-12 10:55:07 +02:00
northbridge PCI subsystem: Drop PCI_64BIT_PREF_MEM option 2015-06-10 05:48:37 +02:00
soc pistachio: add DDR3 initialization code 2015-06-12 20:19:42 +02:00
southbridge AMD PI: remove unuseful ACPI code 2015-06-10 21:02:15 +02:00
superio devicetree: Discriminate device ops scan_bus() 2015-06-04 11:19:01 +02:00
vendorcode vboot: add new firmware indicies 2015-06-09 22:38:51 +02:00
Kconfig lenovo: Hide SMBIOS config 2015-06-11 13:20:56 +02:00