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2f7ed8d775
Select aclk_emmc and clk_emmc source from GPLL, and both to 198MHz, that is GPLL(594MHz) divided by 3. BRANCH=none BUG=chrome-os-partner:51537 TEST=boot kevin rev1 to chromeos prompt from both emmc and sdcard TEST=LoadKernel faster, more than twice as I measured manually. Change-Id: I2580c43b8c79049c3fe16bbf60bfa1a8e0559948 Signed-off-by: Martin Roth <martinroth@google.com> Original-Commit-Id: 5fd37b66dcce77354e1cafab0d6e806d832c08d2 Original-Change-Id: Id22815b302af3204e0e5537af99c1577b09b0877 Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/339152 Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/14855 Tested-by: build bot (Jenkins) Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
100 lines
3.2 KiB
C
100 lines
3.2 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright 2016 Rockchip Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <boardid.h>
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#include <device/device.h>
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#include <gpio.h>
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#include <soc/clock.h>
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#include <soc/grf.h>
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static void configure_emmc(void)
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{
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/* Host controller does not support programmable clock generator.
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* If we don't do this setting, when we use phy to control the
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* emmc clock(when clock exceed 50MHz), it will get wrong clock.
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*
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* Refer to TRM V0.3 Part 1 Chapter 15 PAGE 782 for this register.
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* Please search "_CON11[7:0]" to locate register description.
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*/
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write32(&rk3399_grf->emmccore_con[11], RK_CLRSETBITS(0xff, 0));
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rkclk_configure_emmc();
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}
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static void configure_sdmmc(void)
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{
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gpio_output(GPIO(4, D, 5), 1); /* SDMMC_PWR_EN */
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gpio_output(GPIO(2, A, 2), 1); /* SDMMC_SDIO_PWR_EN */
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/* SDMMC_DET_L is different on Kevin board revision 0. */
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if (IS_ENABLED(CONFIG_BOARD_GOOGLE_KEVIN) && (board_id() == 0))
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gpio_input(GPIO(4, D, 2));
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else
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gpio_input(GPIO(4, D, 0));
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gpio_output(GPIO(2, D, 4), 0); /* Keep the max voltage */
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/*
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* The SD card on this board is connected to port SDMMC0, which is
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* multiplexed with GPIO4B pins 0..5.
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*
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* Disable all pullups on these pins. For pullup configuration
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* register layout stacks banks 2 through 4 together, hence [2] means
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* group 4, [1] means bank B. This register is described on page 342
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* of section 1 of the TRM.
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*
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* Each GPIO pin's pull config takes two bits, writing zero to the
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* field disables pull ups/downs, as described on page 342 of rk3399
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* TRM Version 0.3 Part 1.
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*/
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write32(&rk3399_grf->gpio2_p[2][1], RK_CLRSETBITS(0xfff, 0));
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/*
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* Set all outputs' drive strength to 8 mA. Group 4 bank B driver
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* strength requires three bits per pin. Value of 2 written in that
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* three bit field means '8 mA', as deduced from the kernel code.
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*
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* Thus the six pins involved in SDMMC interface require 18 bits to
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* configure drive strength, but each 32 bit register provides only 16
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* bits for this setting, this covers 5 pins fully and one bit from
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* the 6th pin. Two more bits spill over to the next register. This is
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* described on page 378 of rk3399 TRM Version 0.3 Part 1.
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*/
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write32(&rk3399_grf->gpio4b_e01,
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RK_CLRSETBITS(0xffff,
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(2 << 0) | (2 << 3) |
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(2 << 6) | (2 << 9) | (2 << 12)));
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write32(&rk3399_grf->gpio4b_e2, RK_CLRSETBITS(3, 1));
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/* And now set the multiplexor to enable SDMMC0. */
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write32(&rk3399_grf->iomux_sdmmc, IOMUX_SDMMC);
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}
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static void mainboard_init(device_t dev)
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{
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configure_sdmmc();
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configure_emmc();
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}
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static void mainboard_enable(device_t dev)
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{
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dev->ops->init = &mainboard_init;
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}
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struct chip_operations mainboard_ops = {
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.name = CONFIG_MAINBOARD_PART_NUMBER,
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.enable_dev = mainboard_enable,
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};
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