switch-coreboot/src
Edward O'Callaghan 2d072d415b northbridge/amd/gx2,lx: Treat MSR constant as unsigned long
Clang complains that a signed shift result (0x210000000)
requires 35 bits to represent, but 'int' only has 32 bits.
However, we write the high bits separately and so this is
a spurious warning.

Change-Id: I3e1c57334077feb50004d7b39abff4bd84ca095b
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7673
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2014-12-10 07:06:39 +01:00
..
arch x86: provide symmetry between arm for cache_sync_instructions() 2014-12-09 18:40:50 +01:00
console ipq8064: prepare UART driver for use in coreboot 2014-12-05 20:22:47 +01:00
cpu vendorcode/amd/agesa/fam10: Build as a static library 2014-12-08 06:24:18 +01:00
device ddr3: Plumber DIMM type to parsed structure. 2014-12-07 15:18:41 +01:00
drivers vboot: allow for non-memory-mapped VBOOT regions 2014-12-09 18:41:00 +01:00
ec spi: Factor EC protocol details out of the SPI drivers. 2014-12-09 20:32:06 +01:00
include spi: Eliminate the spi_cs_activate and spi_cs_deactivate functions. 2014-12-09 20:32:18 +01:00
lib x86: provide symmetry between arm for cache_sync_instructions() 2014-12-09 18:40:50 +01:00
mainboard spi: Factor EC protocol details out of the SPI drivers. 2014-12-09 20:32:06 +01:00
northbridge northbridge/amd/gx2,lx: Treat MSR constant as unsigned long 2014-12-10 07:06:39 +01:00
soc spi: Eliminate the spi_cs_activate and spi_cs_deactivate functions. 2014-12-09 20:32:18 +01:00
southbridge spi: Eliminate the spi_cs_activate and spi_cs_deactivate functions. 2014-12-09 20:32:18 +01:00
superio Mark non-executable files non-executable 2014-12-01 17:33:07 +01:00
vendorcode vboot: allow for non-memory-mapped VBOOT regions 2014-12-09 18:41:00 +01:00
Kconfig Kconfig: Remove ACPI_SSDTX_NUM. 2014-12-07 21:06:34 +01:00