mirror of
https://github.com/fail0verflow/switch-coreboot.git
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2cfe260e9c
Bootblock: - Temporary BAR needs to be assigned for SPI device until PCI enumeration is done by ramstage which allocates a new BAR. - Call spi_init to allow bootblock/verstage to write/erase on flash. Ramstage: - spi_init needs to run in ramstage to allow write protect to be disabled for eventlog and NVRAM updates. This needs to be done pretty early so that any init calls(e.g. mainboard_ec_init) writing to flash work properly. Verified with this change that there are no more flash write/erase errors for ELOG/NVRAM. BUG=chrome-os-partner:54283 Change-Id: Iff840e055548485e6521889fcf264a10fb5d9491 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15209 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Tested-by: build bot (Jenkins) Reviewed-on: https://chromium-review.googlesource.com/354991 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org>
148 lines
4.1 KiB
C
148 lines
4.1 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2016 Intel Corp.
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* (Written by Andrey Petrov <andrey.petrov@intel.com> for Intel Corp.)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/cpu.h>
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#include <bootblock_common.h>
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#include <cpu/x86/mtrr.h>
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#include <device/pci.h>
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#include <lib.h>
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#include <soc/iomap.h>
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#include <soc/cpu.h>
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#include <soc/gpio.h>
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#include <soc/northbridge.h>
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#include <soc/pci_devs.h>
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#include <soc/uart.h>
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#include <spi-generic.h>
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#include <timestamp.h>
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static const struct pad_config tpm_spi_configs[] = {
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PAD_CFG_NF(GPIO_106, NATIVE, DEEP, NF3), /* FST_SPI_CS2_N */
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};
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static void tpm_enable(void)
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{
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/* Configure gpios */
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gpio_configure_pads(tpm_spi_configs, ARRAY_SIZE(tpm_spi_configs));
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}
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static void enable_pm_timer(void)
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{
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/* ACPI PM timer emulation */
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msr_t msr;
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/*
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* The derived frequency is calculated as follows:
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* (CTC_FREQ * msr[63:32]) >> 32 = target frequency.
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* Back solve the multiplier so the 3.579545MHz ACPI timer
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* frequency is used.
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*/
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msr.hi = (3579545ULL << 32) / CTC_FREQ;
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/* Set PM1 timer IO port and enable*/
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msr.lo = EMULATE_PM_TMR_EN | (ACPI_PMIO_BASE + R_ACPI_PM1_TMR);
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wrmsr(MSR_EMULATE_PM_TMR, msr);
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}
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void asmlinkage bootblock_c_entry(uint64_t base_timestamp)
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{
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device_t dev = NB_DEV_ROOT;
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/* Set PCI Express BAR */
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pci_io_write_config32(dev, PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS | 1);
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/*
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* Clear TSEG register - TSEG register comes out of reset with a
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* non-zero default value. Clear this register to ensure that there are
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* no surprises in CBMEM handling.
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*/
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pci_write_config32(dev, TSEG, 0);
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dev = P2SB_DEV;
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/* BAR and MMIO enable for IOSF, so that GPIOs can be configured */
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pci_write_config32(dev, PCI_BASE_ADDRESS_0, CONFIG_IOSF_BASE_ADDRESS);
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pci_write_config32(dev, PCI_BASE_ADDRESS_1, 0);
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pci_write_config16(dev, PCI_COMMAND,
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PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
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/* Decode the ACPI I/O port range for early firmware verification.*/
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dev = PMC_DEV;
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pci_write_config16(dev, PCI_BASE_ADDRESS_4, ACPI_PMIO_BASE);
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pci_write_config16(dev, PCI_COMMAND,
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PCI_COMMAND_IO | PCI_COMMAND_MASTER);
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/* Call lib/bootblock.c main */
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bootblock_main_with_timestamp(base_timestamp);
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}
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static void cache_bios_region(void)
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{
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int mtrr;
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uint32_t rom_size, alignment;
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mtrr = get_free_var_mtrr();
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if (mtrr==-1)
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return;
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/* Only the IFD BIOS region is memory mapped (at top of 4G) */
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rom_size = CONFIG_IFD_BIOS_END - CONFIG_IFD_BIOS_START;
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/* Round to power of two */
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alignment = 1 << (log2_ceil(rom_size));
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rom_size = ALIGN_UP(rom_size, alignment);
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set_var_mtrr(mtrr, 4ULL*GiB - rom_size, rom_size, MTRR_TYPE_WRPROT);
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}
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/*
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* Program temporary BAR for SPI in case any of the stages before ramstage need
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* to access SPI MMIO regs. Ramstage will assign a new BAR during PCI
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* enumeration.
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*/
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static void enable_spibar(void)
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{
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device_t dev = SPI_DEV;
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uint8_t val;
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/* Disable Bus Master and MMIO space. */
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val = pci_read_config8(dev, PCI_COMMAND);
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val &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
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pci_write_config8(dev, PCI_COMMAND, val);
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/* Program Temporary BAR for SPI */
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pci_write_config32(dev, PCI_BASE_ADDRESS_0,
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PRERAM_SPI_BASE_ADDRESS |
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PCI_BASE_ADDRESS_SPACE_MEMORY);
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/* Enable Bus Master and MMIO Space */
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val = pci_read_config8(dev, PCI_COMMAND);
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val |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
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pci_write_config8(dev, PCI_COMMAND, val);
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/* Initialize SPI to allow BIOS to write/erase on flash. */
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spi_init();
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}
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void bootblock_soc_early_init(void)
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{
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/* Prepare UART for serial console. */
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if (IS_ENABLED(CONFIG_SOC_UART_DEBUG))
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soc_console_uart_init();
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if (IS_ENABLED(CONFIG_TPM_ON_FAST_SPI))
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tpm_enable();
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enable_pm_timer();
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enable_spibar();
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cache_bios_region();
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}
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