Yen Lin 2b7693d63a t210: Add tegra_lp0_resume code ... BUG=chrome-os-partner:40741 BRANCH=None TEST=tested on Smaug; able to suspend/resume Change-Id: I3e796bee4b1bedfd4cce0a37549108d5271658a6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 207ca26cb2c157c0dcf476c4d4973b4d4ec67cc7 Original-Change-Id: I8565d4cf1632d6d3023aa55b2bff824a092f2c3b Original-Signed-off-by: Yen Lin <yelin@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/277025 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/11018 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)		2015-07-21 21:43:53 +02:00
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acpi	acpi/sata: add generic sata ssdt port generator	2015-06-07 01:24:47 +02:00
arch	arm64: Set LOG_LEVEL=0 for BL31 if coreboot does not use serial	2015-07-21 21:26:52 +02:00
console	consoles: remove unused infrastructure	2015-05-26 19:02:54 +02:00
cpu	indent style fix for lapic_cpu_init.c	2015-07-17 17:53:06 +02:00
device	x86 realmode: Set up the 8254 timer before running option rom	2015-07-16 04:03:45 +02:00
drivers	console: Add UART8250MEM 32bit support	2015-07-21 20:16:48 +02:00
ec	mec: Correct the access mode for short payloads	2015-07-21 21:22:15 +02:00
include	cbfs: hardcode file alignment	2015-07-15 16:34:37 +02:00
lib	cbfs: hardcode file alignment	2015-07-15 16:34:37 +02:00
mainboard	google/cyan: Configure EC_IN_RW signal as gpio input	2015-07-21 21:24:53 +02:00
northbridge	Revert "northbridge/amd/pi: Add support for memory settings"	2015-07-21 19:49:41 +02:00
soc	t210: Add tegra_lp0_resume code	2015-07-21 21:43:53 +02:00
southbridge	amd/hudson: Fix makefile FWM location check	2015-07-21 03:39:50 +02:00
superio	superio/smsc: Add support for SMSC DME1737	2015-07-13 17:11:00 +02:00
vendorcode	cbfs: hardcode file alignment	2015-07-15 16:34:37 +02:00
Kconfig	riscv-emulation: Set stack size to 0 in Kconfig	2015-07-14 16:56:25 +02:00