mirror of
https://github.com/fail0verflow/switch-coreboot.git
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2a605775a6
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@392 f3766cd6-281f-0410-b1cd-43a5c92072e9
78 lines
2.2 KiB
C
78 lines
2.2 KiB
C
/*
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* This file is part of the LinuxBIOS project.
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*
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* Copyright (C) 2007 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <types.h>
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#include <lib.h>
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#include <console.h>
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#include <post_code.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <io.h>
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#include <device/pnp.h>
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#include <string.h>
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#include <msr.h>
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#include <io.h>
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#include <amd_geodelx.h>
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#include <southbridge/amd/cs5536/cs5536.h>
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#include <northbridge/amd/geodelx/raminit.h>
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#include <superio/winbond/w83627hf/w83627hf.h>
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#define SERIAL_DEV 0x30
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#define MANUALCONF 0 /* Do automatic strapped PLL config */
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#define PLLMSRHI 0x00001490 /* manual settings for the PLL */
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#define PLLMSRLO 0x02000030
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#define DIMM0 ((u8) 0xA0)
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#define DIMM1 ((u8) 0xA2)
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int main(void)
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{
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void done_cache_as_ram_main(void);
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void w83627hf_enable_serial(u8 dev, u8 serial, u16 iobase);
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post_code(POST_START_OF_MAIN);
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system_preinit();
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geodelx_msr_init();
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cs5536_early_setup();
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/* NOTE: must do this AFTER the early_setup!
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* it is counting on some early MSR setup
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* for cs5536
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*/
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cs5536_disable_internal_uart();
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w83627hf_enable_serial(0x2e, 0x30, 0x3f8);
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console_init();
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pll_reset(MANUALCONF, PLLMSRHI, PLLMSRLO);
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cpu_reg_init(0, DIMM0, DIMM1);
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sdram_set_registers();
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sdram_set_spd_registers(DIMM0, DIMM1);
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sdram_enable(DIMM0, DIMM1);
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/* Check low memory */
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//ram_check(0x00000000, 640*1024);
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/* Switch from Cache as RAM to real RAM */
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printk(BIOS_SPEW, "Before wbinvd\n");
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__asm__("wbinvd\n");
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printk(BIOS_SPEW, "After wbinvd\n");
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}
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