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28ecbeab88
multiple links. The way this was done in v2 was a big confusing; this way is
less so.
The changes are easy. Getting them right has been hard :-)
First, for a k8 north that has three links, you can name each one as follows:
pci0@18,0
pci1@18,0
pci2@18,0
We have to have the same pcidevfn on these because that is how the k8 works.
But the unit numbers (pci0, pci1, etc.) distinguish them.
The dts will properly generate a "v3 device code"
compatible static tree that puts the links in the right place in the
data structure.
The changes to dts are trivial.
As before, dts nodes with children are understood to be a bridge.
But what if there is a dts entry like this:
pci1@18,0 {/config/("northbridge/amd/k8/pci");};
This entry has no children in the dts.
How does dt compiler know it is a bridge? It can not know unless
we add information to the dts for that northbridge part.
To ensure that all bridge devices are detected, we support the following:
if a dts node for a device has a bridge property, e.g.:
{
device_operations = "k8_ops";
bridge;
};
The dt compiler will treat it as a bridge whether it has children or not.
Why would a device not have children? Because it might be attached to a
pci or other socket, and we don't know at build time if the socket is empty,
or what might be in the socket.
This code has been tested on dbe62 and k8 simnow, and works on each.
It is minimal in size and it does what we need. I hope it resolves our
discussion for now. We might want to improve or change the device code
later but, at this point, forward motion is important -- I'm on a deadline for
a very important demo Oct. 22!
Also included in this patch are new debug prints in k8 north.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@865 f3766cd6-281f-0410-b1cd-43a5c92072e9
118 lines
3.4 KiB
C
118 lines
3.4 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#define _MAINOBJECT
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#include <types.h>
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#include <lib.h>
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#include <console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <string.h>
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#include <msr.h>
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#include <io.h>
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#include <amd_geodelx.h>
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#include <northbridge/amd/geodelx/raminit.h>
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/* #include <device/smbus.h>
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* TODO: figure out how smbus functions should be done. See smbus_ops.c
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*/
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extern int smbus_read_byte(u16 device, u8 address);
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#define MANUALCONF 0 /* Do automatic strapped PLL config */
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#define PLLMSRHI 0x00001490 /* manual settings for the PLL */
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#define PLLMSRLO 0x02000030
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#define DIMM0 ((u8) 0xA0)
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#define DIMM1 ((u8) 0xA2)
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/**
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* Read a byte from the SPD.
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*
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* For this board, that is really just saying 'read a byte from SMBus'.
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* So we use smbus_read_byte(). Nota Bene: leave this here as a function
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* rather than a #define in an obscure location. This function is called
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* only a few dozen times, and it's not performance critical.
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*
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* @param device The device.
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* @param address The address.
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* @return The data from the SMBus packet area or an error of 0xff (i.e. -1).
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*/
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u8 spd_read_byte(u16 device, u8 address)
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{
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u8 spdbyte;
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printk(BIOS_DEBUG, "spd_read_byte dev %04x\n", device);
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spdbyte = smbus_read_byte(device, address);
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printk(BIOS_DEBUG, " addr %02x returns %02x\n", address, spdbyte);
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return spdbyte;
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}
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/**
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* Placeholder in case we ever need it. Since this file is a
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* template for other motherboards, we want this here and we want the
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* call in the right place.
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*/
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static void mb_gpio_init(void)
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{
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/* Early mainboard specific GPIO setup */
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}
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/**
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* main for initram for the AMD DB800 development platform.
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* It might seem that you could somehow do these functions in, e.g., the cpu
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* code, but the order of operations and what those operations are is VERY
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* strongly mainboard dependent. It's best to leave it in the mainboard code.
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*/
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int main(void)
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{
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printk(BIOS_DEBUG, "Hi there from initram (stage1) main!\n");
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post_code(POST_START_OF_MAIN);
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system_preinit();
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printk(BIOS_DEBUG, "done preinit\n");
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mb_gpio_init();
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printk(BIOS_DEBUG, "done gpio init\n");
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pll_reset(MANUALCONF, PLLMSRHI, PLLMSRLO);
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printk(BIOS_DEBUG, "done pll reset\n");
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cpu_reg_init(0, DIMM0, DIMM1, DRAM_UNTERMINATED);
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printk(BIOS_DEBUG, "done cpu reg init\n");
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sdram_set_registers();
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printk(BIOS_DEBUG, "done sdram set registers\n");
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sdram_set_spd_registers(DIMM0, DIMM1);
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printk(BIOS_DEBUG, "done sdram set spd registers\n");
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sdram_enable(DIMM0, DIMM1);
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printk(BIOS_DEBUG, "done sdram enable\n");
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/* Check low memory */
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/*ram_check(0x00000000, 640*1024); */
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printk(BIOS_DEBUG, "stage1 returns\n");
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return 0;
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}
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