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https://github.com/fail0verflow/switch-coreboot.git
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24724235d7
MMCONF was explicitly used here to avoid races of 0xcf8/0xcfc access being non-atomic and/or need to access 4kiB of PCI config space. All these platforms now have MMCONF_SUPPORT_DEFAULT. I liked the style of code in pci_mmio_cfg.h more, and used those to replace the ones in io.h. BUG=None BRANCH=None TEST=None Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17689 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: Ib5e6a451866c95d1edb9060c7f94070830b90e92 Reviewed-on: https://chromium-review.googlesource.com/417941 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
52 lines
1.8 KiB
C
52 lines
1.8 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/io.h>
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#include <stdlib.h>
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#include "nehalem.h"
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#define PCI_DEV_SNB PCI_DEV(0, 0, 0)
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void intel_nehalem_finalize_smm(void)
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{
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pci_or_config16(PCI_DEV_SNB, 0x50, 1 << 0); /* GGC */
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pci_or_config32(PCI_DEV_SNB, 0x5c, 1 << 0); /* DPR */
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pci_or_config32(PCI_DEV_SNB, 0x78, 1 << 10); /* ME */
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pci_or_config32(PCI_DEV_SNB, 0x90, 1 << 0); /* REMAPBASE */
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pci_or_config32(PCI_DEV_SNB, 0x98, 1 << 0); /* REMAPLIMIT */
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pci_or_config32(PCI_DEV_SNB, 0xa0, 1 << 0); /* TOM */
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pci_or_config32(PCI_DEV_SNB, 0xa8, 1 << 0); /* TOUUD */
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pci_or_config32(PCI_DEV_SNB, 0xb0, 1 << 0); /* BDSM */
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pci_or_config32(PCI_DEV_SNB, 0xb4, 1 << 0); /* BGSM */
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pci_or_config32(PCI_DEV_SNB, 0xb8, 1 << 0); /* TSEGMB */
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pci_or_config32(PCI_DEV_SNB, 0xbc, 1 << 0); /* TOLUD */
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MCHBAR32_OR(0x5500, 1 << 0); /* PAVP */
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MCHBAR32_OR(0x5f00, 1 << 31); /* SA PM */
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MCHBAR32_OR(0x6020, 1 << 0); /* UMA GFX */
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MCHBAR32_OR(0x63fc, 1 << 0); /* VTDTRK */
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MCHBAR32_OR(0x6800, 1 << 31);
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MCHBAR32_OR(0x7000, 1 << 31);
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MCHBAR32_OR(0x77fc, 1 << 0);
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/* Memory Controller Lockdown */
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MCHBAR8(0x50fc) = 0x8f;
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/* Read+write the following */
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MCHBAR32(0x6030) = MCHBAR32(0x6030);
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MCHBAR32(0x6034) = MCHBAR32(0x6034);
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MCHBAR32(0x6008) = MCHBAR32(0x6008);
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}
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