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244cf2ecda
The BOOT_BEEP gpio is used to activate the buffer which isolates the I2S signals from PCH while doing a beep from depthcharge. It needs to be lo to deactivate the buffer for audio playback from OS. BUG=chrome-os-partner:47124 BRANCH=None TEST=boot depthcharge & test beep with devbeep. Boot OS and test audio playback. Change-Id: I047513f6cbe9590820dfe3c369161a157864be97 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d0e04d6792a4511630b8111d0f4a64226042f3e6 Original-Change-Id: I0fa8f425ac413798740343823d026c6300c8eef1 Original-Signed-off-by: Rohit Ainapure <rohit.m.ainapure@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/319220 Original-Commit-Ready: Rohit M Ainapure <rohit.m.ainapure@intel.com> Original-Tested-by: Michael Rang <michael.rang@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/12988 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
239 lines
10 KiB
C
Executable file
239 lines
10 KiB
C
Executable file
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2013 Google Inc.
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* Copyright (C) 2015 Intel Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
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* GNU General Public License for more details.
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*/
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#ifndef MAINBOARD_GPIO_H
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#define MAINBOARD_GPIO_H
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#include <soc/gpe.h>
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#include <soc/gpio.h>
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/* EC in RW */
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#define GPIO_EC_IN_RW GPP_C6
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/* BIOS Flash Write Protect */
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#define GPIO_PCH_WP GPP_C23
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/* Memory configuration board straps */
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#define GPIO_MEM_CONFIG_0 GPP_C12
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#define GPIO_MEM_CONFIG_1 GPP_C13
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#define GPIO_MEM_CONFIG_2 GPP_C14
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#define GPIO_MEM_CONFIG_3 GPP_C15
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/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */
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#define GPE_EC_WAKE GPE0_LAN_WAK
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/* GPP_B16 is WLAN_WAKE. GPP_B group is routed to DW0 in the GPE0 block */
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#define GPE_WLAN_WAKE GPE0_DW0_16
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/* GPP_B5 is TOUCHPAD WAKE. GPP_B group is routed to DW0 in the GPE0 block */
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#define GPE_TOUCHPAD_WAKE GPE0_DW0_05
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/* Input device interrupt configuration */
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#define TOUCHPAD_INT_L GPP_B3_IRQ
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#define TOUCHSCREEN_INT_L GPP_E7_IRQ
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#define MIC_INT_L GPP_F10_IRQ
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/* GPP_E16 is EC_SCI_L. GPP_E group is routed to DW2 in the GPE0 block */
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#define EC_SCI_GPI GPE0_DW2_16
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#define EC_SMI_GPI GPP_E15
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/*
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* GPP_E3 is AUDIO_DB_ID.
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* It is a dual purpose GPIO, used for Audio Daughter
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* Board Identification & to control the shutdown mode pin
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* of the Maxim amp.
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*/
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#define AUDIO_DB_ID GPP_E3
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#ifndef __ACPI__
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/* Pad configuration in ramstage. */
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static const struct pad_config gpio_table[] = {
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/* EC_PCH_RCIN */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),
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/* LPC_LAD_0 */ PAD_CFG_NF(GPP_A1, 20K_PU, DEEP, NF1),
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/* LPC_LAD_1 */ PAD_CFG_NF(GPP_A2, 20K_PU, DEEP, NF1),
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/* LPC_LAD_2 */ PAD_CFG_NF(GPP_A3, 20K_PU, DEEP, NF1),
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/* LPC_LAD_3 */ PAD_CFG_NF(GPP_A4, 20K_PU, DEEP, NF1),
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/* LPC_FRAME */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),
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/* LPC_SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
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/* SD_CD_WAKE */ PAD_CFG_GPI(GPP_A7, 20K_PU, DEEP),
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/* LPC_CLKRUN */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
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/* EC_LPC_CLK */ PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1),
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/* PCH_LPC_CLK */ /* GPP_A10 */
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/* EC_HID_INT */ /* GPP_A11 */
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/* ISH_KB_PROX_INT */ PAD_CFG_GPO(GPP_A12, 0, DEEP),
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/* PCH_SUSPWRACB */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),
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/* PM_SUS_STAT */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
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/* PCH_SUSACK */ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),
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/* SD_1P8_SEL */ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
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/* SD_PWR_EN */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1),
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/* ACCEL INTERRUPT */ PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
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/* ISH_GP1 */ /* GPP_A19 */
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/* GYRO_DRDY */ PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1),
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/* FLIP_ACCEL_INT */ PAD_CFG_NF(GPP_A21, NONE, DEEP, NF1),
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/* GYRO_INT */ PAD_CFG_NF(GPP_A22, NONE, DEEP, NF1),
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/* ISH_GP5 */ /* GPP_A23 */
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/* CORE_VID0 */ /* GPP_B0 */
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/* CORE_VID1 */ /* GPP_B1 */
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/* HSJ_MIC_DET */ PAD_CFG_GPI(GPP_B2, NONE, DEEP),
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/* TRACKPAD_INT */ PAD_CFG_GPI_APIC(GPP_B3, NONE, DEEP),
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/* BT_RF_KILL */ PAD_CFG_GPO(GPP_B4, 0, DEEP),
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/* SRCCLKREQ0# */ PAD_CFG_GPI_ACPI_SCI(GPP_B5, NONE, DEEP, YES), /* TOUCHPAD WAKE */
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/* WIFI_CLK_REQ */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1),
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/* KEPLR_CLK_REQ */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1),
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/* SRCCLKREQ3# */ /* GPP_B8 */
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/* SSD_CLK_REQ */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),
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/* SRCCLKREQ5# */ /* GPP_B10 */
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/* MPHY_EXT_PWR_GATE */ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1),
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/* PM_SLP_S0 */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
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/* PCH_PLT_RST */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
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/* PCH_BUZZER */ PAD_CFG_GPI(GPP_B14, NONE, DEEP),
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/* GSPI0_CS# */ /* GPP_B15 */
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/* WLAN_PCIE_WAKE */ PAD_CFG_GPI_ACPI_SCI(GPP_B16, NONE, DEEP, YES),
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/* SSD_PCIE_WAKE */ PAD_CFG_GPI(GPP_B17, NONE, DEEP),
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/* GSPI0_MOSI */ /* GPP_B18 */
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/* CCODEC_SPI_CS */ PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1),
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/* CODEC_SPI_CLK */ PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1),
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/* CODEC_SPI_MISO */ PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1),
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/* CODEC_SPI_MOSI */ PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1),
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/* SM1ALERT# */ PAD_CFG_GPO(GPP_B23, 0, DEEP),
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/* SMB_CLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
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/* SMB_DATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
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/* SMBALERT# */ PAD_CFG_GPO(GPP_C2, 0, DEEP),
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/* M2_WWAN_PWREN */ PAD_CFG_GPO(GPP_C3, 0, DEEP),
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/* SML0DATA */ PAD_CFG_GPI(GPP_C4, NONE, DEEP),
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/* SML0ALERT# */ PAD_CFG_GPO(GPP_C5, 0, DEEP),
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/* EC_IN_RW */ PAD_CFG_GPI(GPP_C6, NONE, DEEP),
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/* USB_CTL */ PAD_CFG_GPO(GPP_C7, 1, DEEP),
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/* UART0_RXD */ /* GPP_C8 */
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/* UART0_TXD */ /* GPP_C9 */
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/* NFC_RST* */ PAD_CFG_GPO(GPP_C10, 0, DEEP),
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/* EN_PP3300_KEPLER */ PAD_CFG_TERM_GPO(GPP_C11, 0, 20K_PD, DEEP),
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/* PCH_MEM_CFG0 */ PAD_CFG_GPI(GPP_C12, NONE, DEEP),
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/* PCH_MEM_CFG1 */ PAD_CFG_GPI(GPP_C13, NONE, DEEP),
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/* PCH_MEM_CFG2 */ PAD_CFG_GPI(GPP_C14, NONE, DEEP),
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/* PCH_MEM_CFG3 */ PAD_CFG_GPI(GPP_C15, NONE, DEEP),
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/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, 5K_PU, DEEP, NF1),
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/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, 5K_PU, DEEP, NF1),
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/* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
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/* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
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/* GD_UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
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/* GD_UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
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/* TCH_PNL_PWREN */ PAD_CFG_GPO(GPP_C22, 1, DEEP),
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/* SPI_WP_STATUS */ PAD_CFG_GPI(GPP_C23, 20K_PU, DEEP),
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/* ITCH_SPI_CS */ /* GPP_D0 */
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/* ITCH_SPI_CLK */ /* GPP_D1 */
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/* ITCH_SPI_MISO_1 */ /* GPP_D2 */
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/* ITCH_SPI_MISO_0 */ /* GPP_D3 */
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/* CAM_FLASH_STROBE */ PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1),
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/* EN_PP3300_DX_EMMC */ PAD_CFG_GPO(GPP_D5, 1, DEEP),
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/* EN_PP1800_DX_EMMC */ PAD_CFG_GPO(GPP_D6, 1, DEEP),
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/* SH_I2C1_SDA */ PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
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/* SH_I2C1_SCL */ PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1),
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PAD_CFG_GPO(GPP_D9, 0, DEEP),
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/* USB_A0_ILIM_SEL */ PAD_CFG_GPO(GPP_D10, 1, DEEP),
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/* USB_A1_ILIM_SEL */ PAD_CFG_GPO(GPP_D11, 1, DEEP),
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/* EN_PP3300_DX_CAM */ PAD_CFG_GPO(GPP_D12, 1, DEEP),
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/* EN_PP1800_DX_AUDIO */PAD_CFG_GPO(GPP_D13, 1, DEEP),
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/* ISH_UART0_TXD */ /* GPP_D14 */
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/* ISH_UART0_RTS */ /* GPP_D15 */
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/* ISH_UART0_CTS */ /* GPP_D16 */
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/* DMIC_CLK_1 */ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),
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/* DMIC_DATA_1 */ PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),
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/* DMIC_CLK_0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
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/* DMIC_DATA_0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
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/* ITCH_SPI_D2 */ /* GPP_D21 */
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/* ITCH_SPI_D3 */ /* GPP_D22 */
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/* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1),
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/* SPI_TPM_IRQ */ PAD_CFG_GPI_APIC(GPP_E0, NONE, DEEP),
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/* SATAXPCIE1 */ /* GPP_E1 */
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/* SSD_PEDET */ PAD_CFG_GPI(GPP_E2, NONE, DEEP),
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/* AUDIO_DB_ID */ PAD_CFG_GPI(GPP_E3, NONE, DEEP),
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/* SSD_SATA_DEVSLP */ PAD_CFG_GPO(GPP_E4, 0, DEEP),
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/* SATA_DEVSLP1 */ /* GPP_E5 */
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/* SATA_DEVSLP2 */ /* GPP_E6 */
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/* TCH_PNL_INTR* */ PAD_CFG_GPI_APIC(GPP_E7, NONE, DEEP),
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/* SATALED# */ /* GPP_E8 */
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/* USB2_OC_0 */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
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/* USB2_OC_1 */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1),
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/* USB2_OC_2 */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1),
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/* USB2_OC_3 */ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1),
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/* DDI1_HPD */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),
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/* DDI2_HPD */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
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/* EC_SMI */ PAD_CFG_GPI_ACPI_SMI(GPP_E15, NONE, DEEP, YES),
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/* EC_SCI */ PAD_CFG_GPI_ACPI_SCI(GPP_E16, NONE, DEEP, YES),
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/* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
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/* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1),
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/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1),
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/* DDPC_CTRLCLK */ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1),
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/* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),
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/* DDPD_CTRLCLK */ PAD_CFG_GPI(GPP_E22, NONE, DEEP),
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/* TCH_PNL_RST */ PAD_CFG_GPO(GPP_E23, 1, DEEP),
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/* I2S2_SCLK */ PAD_CFG_GPI(GPP_F0, NONE, DEEP),
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/* I2S2_SFRM */ PAD_CFG_GPI(GPP_F1, NONE, DEEP),
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/* I2S2_TXD */ PAD_CFG_GPI(GPP_F2, NONE, DEEP),
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/* I2S2_RXD */ PAD_CFG_GPI(GPP_F3, NONE, DEEP),
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/* I2C2_SDA */ /* GPP_F4 */
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/* I2C2_SCL */ /* GPP_F5 */
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/* I2C3_SDA */ /* GPP_F6 */
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/* I2C3_SCL */ /* GPP_F7 */
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/* I2C4_SDA */ PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1),
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/* I2C4_SDA */ PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1),
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/* AUDIO_IRQ */ PAD_CFG_GPI_APIC(GPP_F10, NONE, DEEP),
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/* AUDIO_IRQ */ PAD_CFG_GPI_ACPI_SCI(GPP_F11, NONE, DEEP, YES),
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/* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1),
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/* EMMC_DATA0 */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1),
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/* EMMC_DATA1 */ PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1),
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/* EMMC_DATA2 */ PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1),
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/* EMMC_DATA3 */ PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1),
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/* EMMC_DATA4 */ PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1),
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/* EMMC_DATA5 */ PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1),
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/* EMMC_DATA6 */ PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
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/* EMMC_DATA7 */ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
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/* EMMC_RCLK */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
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/* EMMC_CLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1),
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/* BOOT_BEEP */ PAD_CFG_GPO(GPP_F23, 0, DEEP),
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/* SD_CMD */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1),
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/* SD_DATA0 */ PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1),
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/* SD_DATA1 */ PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1),
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/* SD_DATA2 */ PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1),
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/* SD_DATA3 */ PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1),
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/* SD_CD# */ PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1),
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/* SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1),
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/* SD_WP */ PAD_CFG_NF(GPP_G7, NONE, DEEP, NF1),
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/* PCH_BATLOW */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
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/* EC_PCH_ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1),
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/* EC_PCH_WAKE */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1),
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/* EC_PCH_PWRBTN */ PAD_CFG_NF(GPD3, NONE, DEEP, NF1),
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/* PM_SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
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/* PM_SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
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/* PM_SLP_SA# */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1),
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/* GPD7 */
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/* PM_SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
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/* PCH_SLP_WLAN# */ /* GPD9 */
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/* PM_SLP_S5# */ PAD_CFG_NF(GPD10, NONE, DEEP, NF1),
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/* LANPHYC */ /* GPD11 */
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};
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/* Early pad configuration in romstage. */
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static const struct pad_config early_gpio_table[] = {
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/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* KEPLER */
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/* SPI_WP_STATUS */ PAD_CFG_GPI(GPP_C23, 20K_PU, DEEP),
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/* UART0_CTS# */ PAD_CFG_GPO(GPP_C11, 0, DEEP), /* EN_PP3300_KEPLER */
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};
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#endif
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#endif
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