mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
This patch configures clock for mipi and then
adds mipi driver for support innolux-p079zca
mipi panel in rk3399 scarlet.
BUG=none
BRANCH=none
TEST=none
Change-Id: I7e18b13b1403cb731aa8b5bd214bd35fd5f96637
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: fe122d4dfc
Original-Change-Id: I02475eefb187c619c614b1cd20e97074bc8d917f
Original-Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com>
Original-Reviewed-on: https://review.coreboot.org/19477
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/508773
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
157 lines
4 KiB
C
157 lines
4 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright 2016 Rockchip Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/cache.h>
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#include <arch/mmu.h>
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#include <arch/io.h>
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#include <console/console.h>
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#include <device/device.h>
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#include <delay.h>
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#include <edid.h>
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#include <gpio.h>
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#include <stdlib.h>
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#include <stddef.h>
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#include <string.h>
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#include <soc/addressmap.h>
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#include <soc/clock.h>
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#include <soc/display.h>
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#include <soc/edp.h>
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#include <soc/gpio.h>
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#include <soc/grf.h>
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#include <soc/mmu_operations.h>
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#include <soc/mipi.h>
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#include <soc/soc.h>
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#include <soc/vop.h>
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#include "chip.h"
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static void reset_edp(void)
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{
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/* rst edp */
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write32(&cru_ptr->softrst_con[17],
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RK_SETBITS(1 << 12 | 1 << 13));
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udelay(1);
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write32(&cru_ptr->softrst_con[17],
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RK_CLRBITS(1 << 12 | 1 << 13));
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printk(BIOS_WARNING, "Retrying epd initialization.\n");
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}
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static void rk_get_mipi_mode(struct edid *edid, device_t dev)
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{
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struct soc_rockchip_rk3399_config *conf = dev->chip_info;
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edid->mode.pixel_clock = conf->panel_pixel_clock;
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edid->mode.refresh = conf->panel_refresh;
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edid->mode.ha = conf->panel_ha;
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edid->mode.hbl = conf->panel_hbl;
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edid->mode.hso = conf->panel_hso;
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edid->mode.hspw = conf->panel_hspw;
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edid->mode.va = conf->panel_va;
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edid->mode.vbl = conf->panel_vbl;
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edid->mode.vso = conf->panel_vso;
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edid->mode.vspw = conf->panel_vspw;
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}
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void rk_display_init(device_t dev)
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{
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struct edid edid;
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struct soc_rockchip_rk3399_config *conf = dev->chip_info;
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enum vop_modes detected_mode = VOP_MODE_UNKNOWN;
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int retry_count = 0;
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/* let's use vop0 in rk3399 */
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uint32_t vop_id = 0;
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switch (conf->vop_mode) {
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case VOP_MODE_NONE:
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return;
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case VOP_MODE_EDP:
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printk(BIOS_DEBUG, "Attempting to set up EDP display.\n");
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rkclk_configure_vop_aclk(vop_id, 200 * MHz);
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rkclk_configure_edp(25 * MHz);
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/* select edp signal from vop0 */
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write32(&rk3399_grf->soc_con20, RK_CLRBITS(1 << 5));
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/* select edp clk from SoC internal 24M crystal, otherwise,
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* it will source from edp's 24M clock (that depends on
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* edp vendor, could be unstable)
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*/
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write32(&rk3399_grf->soc_con25, RK_SETBITS(1 << 11));
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retry_edp:
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while (retry_count++ < 3) {
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rk_edp_init();
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if (rk_edp_get_edid(&edid) == 0) {
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detected_mode = VOP_MODE_EDP;
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break;
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}
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if (retry_count == 3) {
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printk(BIOS_WARNING, "Warning: epd initialization failed.\n");
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return;
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} else {
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reset_edp();
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}
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}
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break;
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case VOP_MODE_MIPI:
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printk(BIOS_DEBUG, "Attempting to setup MIPI display.\n");
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rkclk_configure_mipi();
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rkclk_configure_vop_aclk(vop_id, 200 * MHz);
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/* disable turnrequest turndisable forcetxstop forcerxmode */
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write32(&rk3399_grf->soc_con22, RK_CLRBITS(0xffff));
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/* select mipi-dsi0 signal from vop0 */
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write32(&rk3399_grf->soc_con20, RK_CLRBITS(1 << 0));
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rk_get_mipi_mode(&edid, dev);
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detected_mode = VOP_MODE_MIPI;
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break;
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default:
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printk(BIOS_WARNING, "Unsupported vop_mode, aborting.\n");
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return;
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}
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if (rkclk_configure_vop_dclk(vop_id,
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edid.mode.pixel_clock * KHz)) {
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printk(BIOS_WARNING, "config vop err\n");
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return;
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}
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edid_set_framebuffer_bits_per_pixel(&edid,
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conf->framebuffer_bits_per_pixel, 0);
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rkvop_mode_set(vop_id, &edid, detected_mode);
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rkvop_prepare(vop_id, &edid);
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switch (detected_mode) {
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case VOP_MODE_MIPI:
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rk_mipi_prepare(&edid, conf->panel_display_on_mdelay, conf->panel_video_mode_mdelay);
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break;
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case VOP_MODE_EDP:
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/* will enable edp in depthcharge */
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if (rk_edp_prepare()) {
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reset_edp();
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goto retry_edp; /* Rerun entire init sequence */
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}
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break;
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default:
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break;
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}
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mainboard_power_on_backlight();
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set_vbe_mode_info_valid(&edid, (uintptr_t)0);
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return;
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}
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