switch-coreboot/mainboard/amd/db800/dts
Ronald G. Minnich 2f5d7b66a9 1. fix dtc to properly put @x,y in hex, not decimal.
2. Fix trivial bug in dtc -- ioport is 6 chars long, not 3
3. Fix all dts so that the @ parts are now in hex.
4. fix graphics mem in dbs62 to be 16 MB, per artec.

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@700 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-07-30 15:08:25 +00:00

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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007 Ronald G. Minnich <rminnich@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/{
mainboard_vendor = "AMD";
mainboard_name = "DB800";
mainboard_pci_subsystem_vendor = "0x1022";
mainboard_pci_subsystem_device = "0x2323";
cpus { };
apic@0 {
/config/("northbridge/amd/geodelx/apic");
};
domain@0 {
/config/("northbridge/amd/geodelx/domain");
/* Video RAM has to be in 2MB chunks. */
geode_video_mb = "8";
pci@1,0 {
/config/("northbridge/amd/geodelx/pci");
};
pci@f,0 {
/config/("southbridge/amd/cs5536/dts");
/* Interrupt enables for LPC bus.
* Each bit is an IRQ 0-15. */
lpc_serirq_enable = "0x000010da";
/* LPC IRQ polarity. Each bit is an IRQ 0-15. */
lpc_serirq_polarity = "0x0000EF25";
/* 0:continuous 1:quiet */
lpc_serirq_mode = "1";
/* GPIO(0-0x20) for INT D:C:B:A, 0xFF=none.
* See virtual PIC spec. */
enable_gpio_int_route = "0x0D0C0700";
enable_USBP4_device = "1";
};
pci@f,2 {
/config/("southbridge/amd/cs5536/ide");
enable_ide = "1";
};
ioport@2e {
/config/("superio/winbond/w83627hf/dts");
com1enable = "1";
};
};
};