mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
All Intel southbridges implement the same SMBus functions. This patch replaces all these similar and mostly identical implementations with a common file. This also makes i2c block read available to all those southbridges. If the northbridge has to read a lot of SPD bytes sequentially, using this function can reduce the time being spent to read SPD five-fold. Change-Id: I93bb186e04e8c32dff04fc1abe4b5ecbc4c9c962 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19258 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
10 lines
287 B
C
10 lines
287 B
C
#ifndef DEVICE_SMBUS_DEF_H
|
|
#define DEVICE_SMBUS_DEF_H
|
|
|
|
/* Error results are negative success is >= 0 */
|
|
#define SMBUS_ERROR -1
|
|
#define SMBUS_WAIT_UNTIL_READY_TIMEOUT -2
|
|
#define SMBUS_WAIT_UNTIL_DONE_TIMEOUT -3
|
|
#define SMBUS_WAIT_UNTIL_ACTIVE_TIMEOUT -4
|
|
|
|
#endif /* DEVICE_SMBUS_DEF_H */
|