mirror of
https://github.com/fail0verflow/switch-coreboot.git
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16c4145bf5
BUG=None BRANCH=None TEST=None Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16615 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Change-Id: Ibeab5e7fe0a9005e96934b3b43cfb247ef2e2340 Reviewed-on: https://chromium-review.googlesource.com/388285 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
102 lines
3.9 KiB
C
102 lines
3.9 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2014 Edward O'Callaghan <eocallaghan@alterapraxis.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/io.h>
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pnp.h>
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#include "chip.h"
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#include "fintek_internal.h"
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/*
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* The Fintek F71869AD Super I/O Hardware Monitor permits the configuration of
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* three fans individually, where fan1 is typically taken as the CPU fan. Each
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* fan is controlled by the relation:
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*
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* Tfan? = Tnow + (Ta - Tb)*Ct
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*
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* Parameters in this relation are specified in the devicetree.cb.
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*/
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/*
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* Register CR01 ~ CR03 -> Configuration Registers
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* Register CR0A ~ CR0F -> PECI/TSI Control Register
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* Register CR10 ~ CR37 -> Voltage Setting Register
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* Register CR40 ~ CR4E -> PECI 3.0 Command and Register
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* Register CR60 ~ CR8E -> Temperature Setting Register
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* Register CR90 ~ CRDF -> Fan Control Setting Register
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*/
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#define HWM_SMBUS_ADDR 0x08
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#define HWM_SMBUS_CONTROL_REG 0x0A
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#define HWM_FAN_TYPE_SEL_REG 0x94
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#define HWM_FAN1_TEMP_ADJ_RATE_REG 0x95
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#define HWM_FAN_MODE_SEL_REG 0x96
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#define HWM_FAN_FAULT_TIME_REG 0x9F /* bit7 FAN_PROG_SEL */
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#define HWM_FAN1_IDX_RPM_MODE 0xA3
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#define HWM_FAN1_SEG1_SPEED_COUNT 0xAA
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#define HWM_FAN1_SEG2_SPEED_COUNT 0xAB
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#define HWM_FAN1_SEG3_SPEED_COUNT 0xAC
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#define HWM_FAN1_TEMP_MAP_SEL 0xAF
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/* note: multifunc registers need to be tweaked before here */
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void f71869ad_hwm_init(struct device *dev)
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{
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const struct superio_fintek_f71869ad_config *conf = dev->chip_info;
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struct resource *res = find_resource(dev, PNP_IDX_IO0);
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if (!res) {
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printk(BIOS_WARNING, "Super I/O HWM: No HWM resource found.\n");
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return;
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}
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u16 port = res->base; /* data-sheet default base = 0x229 */
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printk(BIOS_INFO,
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"Fintek F71869AD Super I/O HWM: Initializing Hardware Monitor..\n");
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printk(BIOS_DEBUG,
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"Fintek F71869AD Super I/O HWM: Base Address at 0x%x\n", port);
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pnp_enter_conf_mode(dev);
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pnp_set_logical_device(dev);
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/* Fintek F71869AD HWM (ordered) programming sequence. */
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/* SMBus Address p.53 */
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pnp_write_index(port, HWM_SMBUS_ADDR, conf->hwm_smbus_address);
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/* Configure pins 57/58 as PECI_REQ#/PECI (AMD_TSI) p.54 */
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pnp_write_index(port, HWM_SMBUS_CONTROL_REG, conf->hwm_smbus_control_reg);
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/* Tfan1 = Tnow + (Ta - Tb)*Ct where, */
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/* FAN1_TEMP_SEL_DIG, FAN1_TEMP_SEL (Tnow) set to come from CR7Ah p.73 */
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pnp_write_index(port, HWM_FAN1_TEMP_MAP_SEL, conf->hwm_fan1_temp_map_sel);
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/* set FAN_PROG_SEL = 1 */
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pnp_write_index(port, HWM_FAN_FAULT_TIME_REG, 0x8a);
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/* FAN1_BASE_TEMP (Tb) set when FAN_PROG_SEL = 1, p.64-65 */
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pnp_write_index(port, HWM_FAN_TYPE_SEL_REG, conf->hwm_fan_type_sel_reg);
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/* set TFAN1_ADJ_SEL (Ta) p.67 to use CR7Ah p.61 */
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pnp_write_index(port, HWM_FAN_MODE_SEL_REG, conf->hwm_fan_mode_sel_reg);
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/* TFAN1_ADJ_{UP,DOWN}_RATE (Ct = 1/4 up & down) in 0x95 when FAN_PROG_SEL =
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1, p.88 */
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pnp_write_index(port, HWM_FAN1_TEMP_ADJ_RATE_REG, conf->hwm_fan1_temp_adj_rate_reg);
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/* set FAN_PROG_SEL = 0 */
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pnp_write_index(port, HWM_FAN_FAULT_TIME_REG, 0x0a);
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/* FAN1 RPM mode p.70 */
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pnp_write_index(port, HWM_FAN1_IDX_RPM_MODE, conf->hwm_fan1_idx_rpm_mode);
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/* FAN1 Segment X Speed Count */
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pnp_write_index(port, HWM_FAN1_SEG1_SPEED_COUNT, conf->hwm_fan1_seg1_speed_count);
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pnp_write_index(port, HWM_FAN1_SEG2_SPEED_COUNT, conf->hwm_fan1_seg2_speed_count);
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pnp_write_index(port, HWM_FAN1_SEG3_SPEED_COUNT, conf->hwm_fan1_seg3_speed_count);
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pnp_exit_conf_mode(dev);
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}
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