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https://github.com/fail0verflow/switch-coreboot.git
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12f47ecf89
Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://coreboot.org/repository/coreboot-v3@956 f3766cd6-281f-0410-b1cd-43a5c92072e9
41 lines
1.5 KiB
Makefile
41 lines
1.5 KiB
Makefile
##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2007 coresystems GmbH
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## (Written by Stefan Reinauer <stepan@coresystems.de> for coresystems GmbH)
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; either version 2 of the License, or
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## (at your option) any later version.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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$(obj)/device/%.o: $(src)/device/%.c
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$(Q)mkdir -p $(dir $@)
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$(Q)printf " CC $(subst $(shell pwd)/,,$(@))\n"
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$(Q)$(CC) $(INITCFLAGS) -c $< -o $@
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STAGE2_DEVICE_SRC = device.c device_util.c root_device.c \
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pci_device.c pci_ops.c pci_rom.c pnp_device.c pnp_raw.c \
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smbus_ops.c
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# this is only needed on the K8
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ifeq ($(CONFIG_NORTHBRIDGE_AMD_K8),y)
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STAGE2_DEVICE_SRC += hypertransport.c
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endif
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# this is only needed for pcix devices
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ifeq ($(CONFIG_SOUTHBRIDGE_AMD_AMD8132),y)
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STAGE2_DEVICE_SRC += pcix_device.c
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endif
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$(obj)/device/pci_device.o: $(src)/device/pci_device.c $(obj)/statictree.h
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