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https://github.com/fail0verflow/switch-coreboot.git
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122b6d6ce6
membaseconfig0/1 are utterly dependent on the mainboard's particular DRAM setup. This defines their values in the mem_timings struct for pit. Signed-off-by: David Hendricks <dhendrix@chromium.org> Old-Change-Id: Ifd782d1229b2418f8ddbf0bcb3f45cc828ac34b0 Reviewed-on: https://chromium-review.googlesource.com/167488 Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: ron minnich <rminnich@chromium.org> (cherry picked from commit 80eebd5bc0dbb9fabf81f46c25dcd5c5d5747579) exynos5420: necessary updates for DRAM This updates DRAM usage for Exynos5420 so that we can actually use 3.5GB: - Memory chips used with Exynos5420 may have 16 row address lines. Signed-off-by: David Hendricks <dhendrix@chromium.org> Old-Change-Id: I86d1a96d0d1a028587f7655f8de5a2e52165e9d2 Reviewed-on: https://chromium-review.googlesource.com/167489 Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: ron minnich <rminnich@chromium.org> (cherry picked from commit 04bbaf5d8e125166dd689f656d5b37776be01fb1) Squashed two related commits. Change-Id: I4e45bc8a446715897ec21b0160701152fa6b226b Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6613 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
118 lines
3.4 KiB
C
118 lines
3.4 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2012 Samsung Electronics
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* Copyright 2013 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <stddef.h>
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#include <stdlib.h>
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#include <console/console.h>
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#include <cpu/samsung/exynos5420/gpio.h>
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#include <cpu/samsung/exynos5420/dmc.h>
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#include <cpu/samsung/exynos5420/setup.h>
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#include <cpu/samsung/exynos5420/clk.h>
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const struct mem_timings mem_timings = {
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.mem_manuf = MEM_MANUF_SAMSUNG,
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.mem_type = DDR_MODE_DDR3,
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.frequency_mhz = 800,
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.direct_cmd_msr = {
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0x00020018, 0x00030000, 0x00010046, 0x00000d70,
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0x00000c70
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},
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.timing_ref = 0x000000bb,
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.timing_row = 0x6836650f,
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.timing_data = 0x3630580b,
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.timing_power = 0x41000a26,
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.phy0_dqs = 0x08080808,
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.phy1_dqs = 0x08080808,
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.phy0_dq = 0x08080808,
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.phy1_dq = 0x08080808,
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.phy0_tFS = 0x8,
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.phy1_tFS = 0x8,
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.phy0_pulld_dqs = 0xf,
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.phy1_pulld_dqs = 0xf,
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.lpddr3_ctrl_phy_reset = 0x1,
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.ctrl_start_point = 0x10,
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.ctrl_inc = 0x10,
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.ctrl_start = 0x1,
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.ctrl_dll_on = 0x1,
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.ctrl_ref = 0x8,
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.ctrl_force = 0x1a,
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.ctrl_rdlat = 0x0b,
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.ctrl_bstlen = 0x08,
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.fp_resync = 0x8,
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.iv_size = 0x7,
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.dfi_init_start = 1,
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.aref_en = 1,
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.rd_fetch = 0x3,
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.zq_mode_dds = 0x7,
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.zq_mode_term = 0x1,
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.zq_mode_noterm = 1,
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/*
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* Dynamic Clock: Always Running
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* Memory Burst length: 8
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* Number of chips: 1
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* Memory Bus width: 32 bit
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* Memory Type: DDR3
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* Additional Latancy for PLL: 0 Cycle
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*/
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.memcontrol = DMC_MEMCONTROL_CLK_STOP_DISABLE |
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DMC_MEMCONTROL_DPWRDN_DISABLE |
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DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE |
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DMC_MEMCONTROL_TP_DISABLE |
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DMC_MEMCONTROL_DSREF_DISABLE |
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DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(0) |
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DMC_MEMCONTROL_MEM_TYPE_DDR3 |
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DMC_MEMCONTROL_MEM_WIDTH_32BIT |
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DMC_MEMCONTROL_NUM_CHIP_1 |
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DMC_MEMCONTROL_BL_8 |
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DMC_MEMCONTROL_PZQ_DISABLE |
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DMC_MEMCONTROL_MRR_BYTE_7_0,
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/*
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* For channel interleaving, the chip_base needs to be set to
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* half the bus address. So for a base address of 0x2000_0000,
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* the chip_base value is 0x20 without interleaving and 0x10
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* with channel interleaving. See note in section 17.14.
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*/
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.membaseconfig0 = (0x10 << 16) | DMC_CHIP_MASK_1GB,
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.memconfig = DMC_MEMCONFIG_CHIP_MAP_SPLIT |
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DMC_MEMCONFIGx_CHIP_COL_10 |
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DMC_MEMCONFIGx_CHIP_ROW_15 |
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DMC_MEMCONFIGx_CHIP_BANK_8,
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.prechconfig_tp_cnt = 0xff,
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.dpwrdn_cyc = 0xff,
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.dsref_cyc = 0xffff,
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.concontrol = DMC_CONCONTROL_DFI_INIT_START_DISABLE |
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DMC_CONCONTROL_TIMEOUT_LEVEL0 |
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DMC_CONCONTROL_RD_FETCH_DISABLE |
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DMC_CONCONTROL_EMPTY_DISABLE |
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DMC_CONCONTROL_AREF_EN_DISABLE |
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DMC_CONCONTROL_IO_PD_CON_DISABLE,
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.dmc_channels = 1,
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.chips_per_channel = 1,
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.chips_to_configure = 1,
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.send_zq_init = 1,
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.gate_leveling_enable = 1,
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};
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