mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
0d9cd92efb
1. Currenty, boot reason is being added to elog only for some ARM32/ARM64 platforms. Change this so that boot reason is logged by default in elog for all devices which have CHROMEOS selected. 2. Add a new option to select ELOG_WATCHDOG_RESET for the devices that want to add details about watchdog reset in elog. This requires a special region WATCHDOG to be present in the memlayout. 3. Remove calls to elog add boot reason and watchdog reset from mainboards. BUG=chrome-os-partner:55639 Change-Id: I91ff5b158cfd2a0749e7fefc498d8659f7e6aa91 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15897 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
120 lines
3 KiB
C
120 lines
3 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright 2014 Rockchip Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/cache.h>
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#include <arch/io.h>
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#include <boot/coreboot_tables.h>
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#include <console/console.h>
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#include <delay.h>
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#include <device/device.h>
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#include <device/i2c.h>
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#include <edid.h>
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#include <elog.h>
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#include <gpio.h>
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#include <soc/display.h>
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#include <soc/grf.h>
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#include <soc/soc.h>
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#include <soc/pmu.h>
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#include <soc/clock.h>
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#include <soc/rk808.h>
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#include <soc/spi.h>
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#include <soc/i2c.h>
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#include <symbols.h>
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#include <vbe.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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#include <vboot/vboot_common.h>
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#include "board.h"
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static void configure_usb(void)
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{
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gpio_output(GPIO(0, B, 4), 1); /* USB2_PWR_EN */
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}
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static void configure_emmc(void)
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{
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write32(&rk3288_grf->iomux_emmcdata, IOMUX_EMMCDATA);
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write32(&rk3288_grf->iomux_emmcpwren, IOMUX_EMMCPWREN);
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write32(&rk3288_grf->iomux_emmccmd, IOMUX_EMMCCMD);
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gpio_output(GPIO(2, B, 1), 1); /* EMMC_RST_L */
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}
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static void configure_codec(void)
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{
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write32(&rk3288_grf->iomux_i2c2, IOMUX_I2C2); /* CODEC I2C */
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i2c_init(2, 400*KHz); /* CODEC I2C */
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write32(&rk3288_grf->iomux_i2s, IOMUX_I2S);
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write32(&rk3288_grf->iomux_i2sclk, IOMUX_I2SCLK);
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rk808_configure_ldo(6, 1800); /* VCC18_CODEC */
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/* AUDIO IO domain 1.8V voltage selection */
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write32(&rk3288_grf->io_vsel, RK_SETBITS(1 << 6));
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rkclk_configure_i2s(12288000);
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}
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static void configure_3g(void)
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{
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/* Force 3G modem off to avoid confusing the EHCI host and
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* causing problems during enumeration/init */
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gpio_output(GPIO(5, C, 1), 1); /* 3G_SHUTDOWN */
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gpio_output(GPIO(4, D, 2), 0); /* 3G_ON_OFF */
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}
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static void mainboard_init(device_t dev)
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{
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gpio_output(GPIO_RESET, 0);
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configure_usb();
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configure_emmc();
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configure_codec();
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configure_3g();
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/* No video. */
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/* If recovery mode is detected, reduce frequency and voltage to reduce
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* heat in case machine is left unattended. chrome-os-partner:41201. */
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if (vboot_recovery_mode_enabled()) {
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printk(BIOS_DEBUG, "Reducing APLL freq for recovery mode.\n");
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rkclk_configure_cpu(APLL_600_MHZ);
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rk808_configure_buck(1, 900);
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}
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}
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static void mainboard_enable(device_t dev)
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{
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dev->ops->init = &mainboard_init;
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}
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struct chip_operations mainboard_ops = {
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.enable_dev = mainboard_enable,
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};
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void lb_board(struct lb_header *header)
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{
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struct lb_range *dma;
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dma = (struct lb_range *)lb_new_record(header);
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dma->tag = LB_TAB_DMA;
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dma->size = sizeof(*dma);
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dma->range_start = (uintptr_t)_dma_coherent;
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dma->range_size = _dma_coherent_size;
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}
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void mainboard_power_on_backlight(void)
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{
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return;
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}
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