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BUG=None BRANCH=None TEST=None Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16851 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Change-Id: Ib06ecd083f00c74f1d227368811729d2944dd1ef Reviewed-on: https://chromium-review.googlesource.com/393293 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
120 lines
3.4 KiB
C
120 lines
3.4 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me@gmail.com>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/io.h>
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#include <console/console.h>
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#include <device/pci.h>
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#include <device/pciexp.h>
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#include <device/pci_ids.h>
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#include "vx900.h"
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/**
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* @file vx900/pcie.c
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*
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* STATUS:
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* We do part of the sequence to initialize the PCIE link. The problem is that
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* the reset signal for each slot is connected to a GPO pin, but We don't know
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* which GPO pin. We need to figure out which GPIO pin is hooked to which slot,
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* and have a mechanism to specify this per-mainboard (devicetree.cb).
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*
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* There is currently no timeout detection mechanism for when a link comes up.
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* If the link never comes up, we hang.
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*/
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static void vx900_pcie_link_init(device_t dev)
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{
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u8 reg8;
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u32 reg32;
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u8 fn = dev->path.pci.devfn & 0x07;
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/* Step 1 : Check for presence of PCIE device */
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reg8 = pci_read_config8(dev, 0x5a);
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if (reg8 & (1 << 6))
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printk(BIOS_DEBUG, "Card detected in PEX%i\n", fn);
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else
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return;
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/* Step 2: Wait for device to enter L0 state */
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/* FIXME: implement timeout detection */
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while (0x8a != pci_read_config8(dev, 0x1c3));
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/* Step 3: Clear PCIe error status, then check for failures */
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pci_write_config32(dev, 0x104, 0xffffffff);
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reg32 = pci_read_config32(dev, 0x104);
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if (0 != reg32) {
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printk(BIOS_DEBUG, "PEX init error. flags 0x%.8x\n", reg32);
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return;
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}
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pci_write_config32(dev, 0x110, 0xffffffff);
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reg32 = pci_read_config32(dev, 0x110);
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if (0 != reg32)
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printk(BIOS_DEBUG, "PEX errors. flags 0x%.8x\n", reg32);
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pci_write_config8(dev, 0xa4, 0xff);
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if (pci_read_config8(dev, 0x4a) & (1 << 3))
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printk(BIOS_DEBUG, "Unsupported request detected.\n");
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pci_write_config8(dev, 0x15a, 0xff);
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if (pci_read_config8(dev, 0x15a) & (1 << 1))
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printk(BIOS_DEBUG, "Negotiation pending.\n");
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/* Step 4: Read vendor ID */
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/* FIXME: Do we want to run through the whole sequence and delay boot
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* by several seconds if the device does not respond properly the first
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* time? */
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}
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static void vx900_pex_dev_set_resources(device_t dev)
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{
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assign_resources(dev->link_list);
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}
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static void vx900_pex_init(device_t dev)
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{
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/* FIXME: For some reason, PEX0 hangs on init. Find issue, fix it. */
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if ((dev->path.pci.devfn & 0x7) == 0)
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return;
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vx900_pcie_link_init(dev);
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}
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static struct device_operations vx900_pex_ops = {
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.read_resources = pci_bus_read_resources,
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.set_resources = vx900_pex_dev_set_resources,
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.enable_resources = pci_bus_enable_resources,
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.init = vx900_pex_init,
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.scan_bus = pciexp_scan_bridge,
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.reset_bus = pci_bus_reset,
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};
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static const unsigned short pci_device_ids[] = {
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PCI_DEVICE_ID_VIA_VX900_PEX1,
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PCI_DEVICE_ID_VIA_VX900_PEX2,
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PCI_DEVICE_ID_VIA_VX900_PEX3,
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PCI_DEVICE_ID_VIA_VX900_PEX4,
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0,
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};
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static const struct pci_driver pex_driver __pci_driver = {
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.ops = &vx900_pex_ops,
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.vendor = PCI_VENDOR_ID_VIA,
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.devices = pci_device_ids,
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};
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