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https://github.com/fail0verflow/switch-coreboot.git
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089b88c165
This claim is useless when done before EHCI controller reset. Code in usbdebug_init_() already sets this properly after reset, see use of DBGP_OWNER. Change-Id: Ic17493fe4edbbbed6ebcbef35a264fbf188f1fba Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4709 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
76 lines
2.1 KiB
C
76 lines
2.1 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2009 coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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// Use simple device model for this file even in ramstage
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#define __SIMPLE_DEVICE__
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#include <stdint.h>
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#include <arch/io.h>
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#include <console/console.h>
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#include <device/pci_ehci.h>
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#include <device/pci_def.h>
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pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx)
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{
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u32 class;
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pci_devfn_t dev;
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#if CONFIG_HAVE_USBDEBUG_OPTIONS
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if (hcd_idx==2)
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dev = PCI_DEV(0, 0x1a, 0);
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else
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dev = PCI_DEV(0, 0x1d, 0);
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#else
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dev = PCI_DEV(0, 0x1d, 7);
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#endif
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class = pci_read_config32(dev, PCI_CLASS_REVISION) >> 8;
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#if CONFIG_HAVE_USBDEBUG_OPTIONS
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if (class != PCI_EHCI_CLASSCODE) {
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/* If we enter here before RCBA programming, EHCI function may
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* appear with the highest function number instead.
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*/
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dev |= PCI_DEV(0, 0, 7);
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class = pci_read_config32(dev, PCI_CLASS_REVISION) >> 8;
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}
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#endif
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if (class != PCI_EHCI_CLASSCODE)
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return 0;
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return dev;
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}
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/* Required for successful build, but currently empty. */
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void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port)
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{
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/* Not needed, the ICH* southbridges hardcode physical USB port 1. */
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}
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void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base)
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{
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/* Bail out. No console to complain in. */
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if (!dev)
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return;
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/* Set the EHCI BAR address. */
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pci_write_config32(dev, EHCI_BAR_INDEX, base);
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/* Enable access to the EHCI memory space registers. */
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pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
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}
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