mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
southbridge drivers in Kconfig. * It includes initial superio code as well, but there is at least one error in the pnp_device.c/superio scenario left * Fixed biosemu.c, vm86.c, pnp_device.c (sort of) * Enable vm86 instead of x86emu per default for vga init for now. This makes VGA in qemu work. There might be a bug in x86emu or the compiler I am using. (gcc version 4.1.2 20070115 (prerelease) (SUSE Linux)) * Import isa-dma.c, keyboard.c and i8259.c from v2 /pc80, which was taken from LinuxBIOSv1 released from LANL under release LA-CC Number 00-34 and using parts from the Linux kernel. This patch makes vga and keyboard work in qemu. Yippie Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@260 f3766cd6-281f-0410-b1cd-43a5c92072e9
139 lines
4.6 KiB
C
139 lines
4.6 KiB
C
/*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*
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*/
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <device/pci_ops.h>
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#include <string.h>
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#define CONFIG_CONSOLE_VGA 1
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#define CONFIG_CONSOLE_VGA_MULTI 0
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struct rom_header * pci_rom_probe(struct device *dev)
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{
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unsigned long rom_address;
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struct rom_header *rom_header;
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struct pci_data *rom_data;
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if (dev->on_mainboard) {
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// in case some device PCI_ROM_ADDRESS can not be set or readonly
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rom_address = dev->rom_address;
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} else {
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rom_address = pci_read_config32(dev, PCI_ROM_ADDRESS);
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}
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if (rom_address == 0x00000000 || rom_address == 0xffffffff) {
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return NULL;
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}
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printk(BIOS_DEBUG, "ROM address for %s = %x\n", dev_path(dev), rom_address);
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if(!dev->on_mainboard) {
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/* enable expansion ROM address decoding */
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pci_write_config32(dev, PCI_ROM_ADDRESS,
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rom_address|PCI_ROM_ADDRESS_ENABLE);
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}
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rom_header = (struct rom_header *)rom_address;
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printk(BIOS_SPEW, "PCI Expansion ROM, signature 0x%04x, INIT size 0x%04x, data ptr 0x%04x\n",
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le32_to_cpu(rom_header->signature),
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rom_header->size * 512, le32_to_cpu(rom_header->data));
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if (le32_to_cpu(rom_header->signature) != PCI_ROM_HDR) {
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printk(BIOS_ERR, "Incorrect Expansion ROM Header Signature %04x\n",
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le32_to_cpu(rom_header->signature));
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return NULL;
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}
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rom_data = (unsigned char *) rom_header + le32_to_cpu(rom_header->data);
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printk(BIOS_SPEW, "PCI ROM Image, Vendor %04x, Device %04x,\n",
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rom_data->vendor, rom_data->device);
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if (dev->vendor != rom_data->vendor || dev->device != rom_data->device) {
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printk(BIOS_ERR, "Device or Vendor ID mismatch Vendor %04x, Device %04x\n",
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rom_data->vendor, rom_data->device);
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return NULL;
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}
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printk(BIOS_SPEW, "PCI ROM Image, Class Code %04x%02x, Code Type %02x\n",
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rom_data->class_hi, rom_data->class_lo,
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rom_data->type);
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if (dev->class != ((rom_data->class_hi << 8) | rom_data->class_lo)) {
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printk(BIOS_DEBUG, "Class Code mismatch ROM %08x, dev %08x\n",
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(rom_data->class_hi << 8) | rom_data->class_lo, dev->class);
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//return NULL;
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}
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return rom_header;
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}
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static void *pci_ram_image_start = (void *)PCI_RAM_IMAGE_START;
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#ifndef GO_AWAY
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int vga_inited;
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struct device *vga_pri;
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#endif
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#if CONFIG_CONSOLE_VGA == 1
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extern int vga_inited; // defined in vga_console.c
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#if CONFIG_CONSOLE_VGA_MULTI == 0
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extern struct device *vga_pri; // the primary vga device, defined in device.c
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#endif
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#endif
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struct rom_header *pci_rom_load(struct device *dev, struct rom_header *rom_header)
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{
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struct pci_data * rom_data;
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unsigned long rom_address;
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unsigned int rom_size;
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unsigned int image_size=0;
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rom_address = pci_read_config32(dev, PCI_ROM_ADDRESS);
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do {
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rom_header = (unsigned char *) rom_header + image_size; // get next image
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rom_data = (unsigned char *) rom_header + le32_to_cpu(rom_header->data);
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image_size = le32_to_cpu(rom_data->ilen) * 512;
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} while ((rom_data->type!=0) && (rom_data->indicator!=0)); // make sure we got x86 version
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if(rom_data->type!=0) return NULL;
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rom_size = rom_header->size * 512;
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if (PCI_CLASS_DISPLAY_VGA == rom_data->class_hi) {
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#if CONFIG_CONSOLE_VGA == 1
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#if CONFIG_CONSOLE_VGA_MULTI == 0
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//if (dev != vga_pri) return NULL; // only one VGA supported
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#endif
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printk(BIOS_DEBUG, "Copying VGA ROM image from 0x%x to 0x%x, 0x%x bytes\n",
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rom_header, PCI_VGA_RAM_IMAGE_START, rom_size);
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memcpy((void *)PCI_VGA_RAM_IMAGE_START, rom_header, rom_size);
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vga_inited = 1;
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return (struct rom_header *) (PCI_VGA_RAM_IMAGE_START);
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#endif
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} else {
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printk(BIOS_DEBUG, "Copying non-VGA ROM image from 0x%x to 0x%x, 0x%x bytes\n",
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rom_header, pci_ram_image_start, rom_size);
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memcpy(pci_ram_image_start, rom_header, rom_size);
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pci_ram_image_start += rom_size;
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return (struct rom_header *) (pci_ram_image_start-rom_size);
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}
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/* disable expansion ROM address decoding */
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pci_write_config32(dev, PCI_ROM_ADDRESS, rom_address & ~PCI_ROM_ADDRESS_ENABLE);
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return NULL;
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}
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