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01464a69b8
Initial files to support the Intel Skylake RVP3 Matches chromium tree at 927026db This board uses the Skylake FSP 1.1 image and does not build without the FspUpdVpd.h file. BRANCH=none BUG=None TEST=Build and run on sklrvp Change-Id: I5e7fff8f62a737e627e25c1e03e343d6167041ea Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10343 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
52 lines
891 B
Text
52 lines
891 B
Text
if BOARD_INTEL_SKLRVP
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config BOARD_SPECIFIC_OPTIONS # dummy
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def_bool y
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select BOARD_ROMSIZE_KB_16384
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select CACHE_ROM
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select CHROMEOS
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select CHROMEOS_RAMOOPS_DYNAMIC
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select CHROMEOS_VBNV_CMOS
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select HAVE_ACPI_RESUME
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select HAVE_ACPI_TABLES
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select HAVE_OPTION_TABLE
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select HAVE_SMI_HANDLER
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select MAINBOARD_HAS_CHROMEOS
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select MARK_GRAPHICS_MEM_WRCOMB
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select MMCONF_SUPPORT
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select MONOTONIC_TIMER_MSR
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select INTEL_PCH_UART_CONSOLE
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select SOC_INTEL_SKYLAKE
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select VBOOT_DYNAMIC_WORK_BUFFER
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select VIRTUAL_DEV_SWITCH
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select LID_SWITCH
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config IRQ_SLOT_COUNT
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int
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default 18
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config BOOT_MEDIA_SPI_BUS
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int
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default 0
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config INTEL_PCH_UART_CONSOLE_NUMBER
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hex
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default 2
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config MAINBOARD_DIR
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string
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default "intel/sklrvp"
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config MAINBOARD_PART_NUMBER
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string
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default "Skylake RVP"
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config MAX_CPUS
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int
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default 8
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config VBOOT_RAMSTAGE_INDEX
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hex
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default 0x3
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endif
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