mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
00c8c4a316
This updates the code for the AMD SR5650 and SB700 southbridges. Among other things, it changes the romstage.c files by replacing a .C file include with a pair of .H file includes. The .C file is now added to the romstage in the SB700 or SR5650 Makefile.inc. file to the romstage and ramstage elements. This particular change affects all mainboards that use the SB700, and their changes are include herein. These mainboards are: Advansus a785e, AMD Mahogany, Mahogany-fam10, Tilapia-fam10, Asrock 939a785gmh, Asus m4a78-em, m4a785-m, Gigabyte ma785gm, Iei Kino-780am2-fam10 Jetway pa78vm5 Supermicro h8scm_fam10 The nuvoton/wpcm450 earlysetup interface is changed because the file is no longer included in the mainboard romstage.c files. Change-Id: I502c0b95a7b9e7bb5dd81d03902bbc2143257e33 Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Signed-off-by: efdesign98 <efdesign98@gmail.com> Reviewed-on: http://review.coreboot.org/107 Tested-by: build bot (Jenkins) Reviewed-by: Kerry She <shekairui@gmail.com> Reviewed-by: Marc Jones <marcj303@gmail.com>
124 lines
4.1 KiB
C
Executable file
124 lines
4.1 KiB
C
Executable file
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2010 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef __SR5650_H__
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#define __SR5650_H__
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#include <stdint.h>
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#include <device/pci_ids.h>
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#include "chip.h"
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#include "rev.h"
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typedef struct __PCIE_CFG__ {
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u16 Config;
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u8 ResetReleaseDelay;
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u8 Gfx0Width;
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u8 Gfx1Width;
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u8 GfxPayload;
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u8 GppPayload;
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u16 PortDetect;
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u8 PortHp; /* hot plug */
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u16 DbgConfig;
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u32 DbgConfig2;
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u8 GfxLx;
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u8 GppLx;
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u8 NBSBLx;
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u8 PortSlotInit;
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u8 Gfx0Pwr;
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u8 Gfx1Pwr;
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u8 GppPwr;
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} PCIE_CFG;
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/* PCIE config flags */
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#define PCIE_DUALSLOT_CONFIG (1 << 0)
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#define PCIE_OVERCLOCK_ENABLE (1 << 1)
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#define PCIE_GPP_CLK_GATING (1 << 2)
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#define PCIE_ENABLE_STATIC_DEV_REMAP (1 << 3)
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#define PCIE_OFF_UNUSED_GFX_LANES (1 << 4)
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#define PCIE_OFF_UNUSED_GPP_LANES (1 << 5)
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#define PCIE_DISABLE_HIDE_UNUSED_PORTS (1 << 7)
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#define PCIE_GFX_CLK_GATING (1 << 11)
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#define PCIE_GFX_COMPLIANCE (1 << 14)
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#define PCIE_GPP_COMPLIANCE (1 << 15)
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/* -------------------- ----------------------
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* NBMISCIND
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------------------- -----------------------*/
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#define PCIE_LINK_CFG 0x8
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#define PCIE_NBCFG_REG7 0x37
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#define STRAPS_OUTPUT_MUX_7 0x67
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#define STRAPS_OUTPUT_MUX_A 0x6a
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/* -------------------- ----------------------
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* PCIEIND
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------------------- -----------------------*/
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#define PCIE_CI_CNTL 0x20
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#define PCIE_LC_LINK_WIDTH 0xa2
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#define PCIE_LC_STATE0 0xa5
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#define PCIE_VC0_RESOURCE_STATUS 0x12a /* 16bit read only */
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#define PCIE_CORE_INDEX_SB (0x05 << 16) /* see rpr 4.3.2.2, bdg 2.1 */
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#define PCIE_CORE_INDEX_GPP1 (0x04 << 16)
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#define PCIE_CORE_INDEX_GPP2 (0x06 << 16)
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#define PCIE_CORE_INDEX_GPP1_GPP2 (0x00 << 16)
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#define PCIE_CORE_INDEX_GPP3a (0x07 << 16)
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#define PCIE_CORE_INDEX_GPP3b (0x03 << 16)
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/* contents of PCIE_VC0_RESOURCE_STATUS */
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#define VC_NEGOTIATION_PENDING (1 << 1)
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#define LC_STATE_RECONFIG_GPPSB 0x10
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/* ------------------------------------------------
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* Global variable
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* ------------------------------------------------- */
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extern PCIE_CFG AtiPcieCfg;
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/* ----------------- export funtions ----------------- */
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u32 nbpcie_p_read_index(device_t dev, u32 index);
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void nbpcie_p_write_index(device_t dev, u32 index, u32 data);
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u32 nbpcie_ind_read_index(device_t nb_dev, u32 index);
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void nbpcie_ind_write_index(device_t nb_dev, u32 index, u32 data);
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u32 pci_ext_read_config32(device_t nb_dev, device_t dev, u32 reg);
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void pci_ext_write_config32(device_t nb_dev, device_t dev, u32 reg, u32 mask, u32 val);
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void sr5650_set_tom(device_t nb_dev);
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void ProgK8TempMmioBase(u8 in_out, u32 pcie_base_add, u32 mmio_base_add);
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void enable_pcie_bar3(device_t nb_dev);
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void disable_pcie_bar3(device_t nb_dev);
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void enable_sr5650_dev8(void);
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void sr5650_htinit(void);
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void sr5650_early_setup(void);
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void sr5650_before_pci_init(void);
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void sr5650_enable(device_t dev);
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void sr5650_gpp_sb_init(device_t nb_dev, device_t dev, u32 port);
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void sr5650_gfx_init(device_t nb_dev, device_t dev, u32 port);
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void avoid_lpc_dma_deadlock(device_t nb_dev, device_t sb_dev);
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void config_gpp_core(device_t nb_dev, device_t sb_dev);
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void PcieReleasePortTraining(device_t nb_dev, device_t dev, u32 port);
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u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port);
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void pcie_config_misc_clk(device_t nb_dev);
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void fam10_optimization(void);
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void sr5650_disable_pcie_bridge(void);
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u32 get_vid_did(device_t dev);
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void sr5650_nb_pci_table(device_t nb_dev);
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void init_gen2(device_t nb_dev, device_t dev, u8 port);
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void sr56x0_lock_hwinitreg(void);
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#endif /* SR5650_H */
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