mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
4f27904291
Given a specification of bitfields defined e.g. as follows:
specfile:
{
"field1" : 8,
"field2" : 4,
"field3" : 4
}
and a set of values for setting defaults:
setterfile:
{
"field1" = 0xff,
"field2" = 0xf,
"field3" = 0xf
}
You can generate a binary packed blob as follows:
./blobtool specfile setterfile binaryoutput
binaryoutput: ff ff
The reverse is also possible, i.e. you can regenerate the setter:
./blobtool -d specfile binaryoutput setterorig
setterorig:
# AUTOGENERATED SETTER BY BLOBTOOL
{
"field1" = 0xff,
"field2" = 0xf,
"field3" = 0xf
}
This tool comes with spec/set files for X200 flash descriptor
and ICH9M GbE region, and can be extended or used to decompile
other data blobs with known specs.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ie8421c67f404631376d83e26f18301b34881cb5a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 0685322f4a
Original-Change-Id: I744d6b421003feb4fc460133603af7e6bd80b1d6
Original-Signed-off-by: Damien Zammit <damien@zamaudio.com>
Original-Reviewed-on: https://review.coreboot.org/17445
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Jonathan Neuschfer <j.neuschaefer@gmx.net>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/438059
187 lines
4.3 KiB
Python
187 lines
4.3 KiB
Python
#
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# Copyright (C) 2014 Steve Shenton <sgsit@libreboot.org>
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# Copyright (C) 2014, 2015 Leah Rowe <info@minifree.org>
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# Copyright (C) 2017 Damien Zammit <damien@zamaudio.com>
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#
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# This program is free software: you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation, either version 3 of the License, or
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# (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# Info on flash descriptor (page 845 onwards):
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#
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# http://www.intel.co.uk/content/dam/doc/datasheet/io-controller-hub-9-datasheet.pdf
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# Flash Descriptor SPEC for GM45/ICH9M
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{
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# Signature for descriptor mode
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"fd_signature" : 32,
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# Flash map registers
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"flmap0_fcba" : 8,
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"flmap0_nc" : 2,
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"flmap0_reserved0" : 6,
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"flmap0_frba" : 8,
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"flmap0_nr" : 3,
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"flmap0_reserved1" : 5,
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"flmap1_fmba" : 8,
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"flmap1_nm" : 3,
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"flmap1_reserved" : 5,
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"flmap1_fisba" : 8,
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"flmap1_isl" : 8,
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"flmap2_fmsba" : 8,
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"flmap2_msl" : 8,
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"flmap2_reserved" : 16,
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# Component section
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"flcomp_density1" : 3,
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"flcomp_density2" : 3,
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"flcomp_reserved0" : 2,
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"flcomp_reserved1" : 8,
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"flcomp_reserved2" : 1,
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"flcomp_readclockfreq" : 3,
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"flcomp_fastreadsupp" : 1,
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"flcomp_fastreadfreq" : 3,
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"flcomp_w_eraseclkfreq" : 3,
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"flcomp_r_statclkfreq" : 3,
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"flcomp_reserved3" : 2,
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"flill" : 32,
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"flbp" : 32,
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"comp_padding"[36] : 8,
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# Region section
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"flreg0_base" : 13,
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"flreg0_reserved0" : 3,
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"flreg0_limit" : 13,
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"flreg0_reserved1" : 3,
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"flreg1_base" : 13,
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"flreg1_reserved0" : 3,
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"flreg1_limit" : 13,
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"flreg1_reserved1" : 3,
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"flreg2_base" : 13,
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"flreg2_reserved0" : 3,
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"flreg2_limit" : 13,
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"flreg2_reserved1" : 3,
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"flreg3_base" : 13,
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"flreg3_reserved0" : 3,
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"flreg3_limit" : 13,
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"flreg3_reserved1" : 3,
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"flreg4_base" : 13,
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"flreg4_reserved0" : 3,
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"flreg4_limit" : 13,
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"flreg4_reserved1" : 3,
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"flreg_padding"[12] : 8,
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# Master access section
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# 1: Host CPU/BIOS
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"flmstr1_requesterid" : 16,
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"flmstr1_r_fd" : 1,
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"flmstr1_r_bios" : 1,
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"flmstr1_r_me" : 1,
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"flmstr1_r_gbe" : 1,
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"flmstr1_r_pd" : 1,
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"flmstr1_r_reserved" : 3,
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"flmstr1_w_fd" : 1,
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"flmstr1_w_bios" : 1,
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"flmstr1_w_me" : 1,
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"flmstr1_w_gbe" : 1,
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"flmstr1_w_pd" : 1,
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"flmstr1_w_reserved" : 3,
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# 2: ME
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"flmstr2_requesterid" : 16,
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"flmstr2_r_fd" : 1,
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"flmstr2_r_bios" : 1,
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"flmstr2_r_me" : 1,
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"flmstr2_r_gbe" : 1,
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"flmstr2_r_pd" : 1,
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"flmstr2_r_reserved" : 3,
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"flmstr2_w_fd" : 1,
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"flmstr2_w_bios" : 1,
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"flmstr2_w_me" : 1,
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"flmstr2_w_gbe" : 1,
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"flmstr2_w_pd" : 1,
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"flmstr2_w_reserved" : 3,
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# 3: GbE
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"flmstr3_requesterid" : 16,
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"flmstr3_r_fd" : 1,
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"flmstr3_r_bios" : 1,
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"flmstr3_r_me" : 1,
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"flmstr3_r_gbe" : 1,
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"flmstr3_r_pd" : 1,
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"flmstr3_r_reserved" : 3,
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"flmstr3_w_fd" : 1,
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"flmstr3_w_bios" : 1,
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"flmstr3_w_me" : 1,
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"flmstr3_w_gbe" : 1,
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"flmstr3_w_pd" : 1,
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"flmstr3_w_reserved" : 3,
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"flmstr_padding"[148] : 8,
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# ICHSTRAP0
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"ich0_medisable" : 1,
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"ich0_reserved0" : 6,
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"ich0_tcomode" : 1,
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"ich0_mesmbusaddr" : 7,
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"ich0_bmcmode" : 1,
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"ich0_trippointsel" : 1,
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"ich0_reserved1" : 2,
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"ich0_integratedgbe" : 1,
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"ich0_lanphy" : 1,
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"ich0_reserved2" : 3,
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"ich0_dmireqiddisable" : 1,
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"ich0_me2smbusaddr" : 7,
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# ICHSTRAP1
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"ich1_dynclk_nmlink" : 1,
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"ich1_dynclk_smlink" : 1,
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"ich1_dynclk_mesmbus" : 1,
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"ich1_dynclk_sst" : 1,
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"ich1_reserved0" : 4,
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"ich1_nmlink_npostreqs" : 1,
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"ich1_reserved1" : 7,
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"ich1_reserved2" : 16,
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"ichstrap_padding"[248] : 8,
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# MCHSTRAP0
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"mch0_medisable" : 1,
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"mch0_mebootfromflash" : 1,
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"mch0_tpmdisable" : 1,
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"mch0_reserved0" : 3,
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"mch0_spifingerprinton" : 1,
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# Alternate disable - allows ME to perform chipset
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# init functions but disables FW apps such as AMT
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"mch0_mealtdisable" : 1,
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"mch0_reserved1" : 8,
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"mch0_reserved2" : 16,
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"mchstrap_padding"[3292]: 8,
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# ME VSCC Table
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"mevscc_jid0" : 32,
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"mevscc_vscc0" : 32,
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"mevscc_jid1" : 32,
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"mevscc_vscc1" : 32,
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"mevscc_jid2" : 32,
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"mevscc_vscc2" : 32,
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"mevscc_padding"[4] : 8,
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# Descriptor Map 2 Record
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"mevscc_tablebase" : 8,
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"mevscc_tablelength" : 8,
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"mevscc_reserved" : 16,
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# OEM section
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"oem_magic"[8] : 8,
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"oem_padding"[248] : 8
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}
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