mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
539a101e1b
hardware and have a specific size. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://coreboot.org/repository/coreboot-v3@1069 f3766cd6-281f-0410-b1cd-43a5c92072e9
274 lines
6.8 KiB
C
274 lines
6.8 KiB
C
/*
|
|
* This file is part of the coreboot project.
|
|
*
|
|
* Copyright (C) 2004 Tyan Computer
|
|
* Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer.
|
|
* Copyright (C) 2006,2007 AMD
|
|
* Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify
|
|
* it under the terms of the GNU General Public License as published by
|
|
* the Free Software Foundation; either version 2 of the License, or
|
|
* (at your option) any later version.
|
|
*
|
|
* This program is distributed in the hope that it will be useful,
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
* GNU General Public License for more details.
|
|
*
|
|
* You should have received a copy of the GNU General Public License
|
|
* along with this program; if not, write to the Free Software
|
|
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
|
*/
|
|
|
|
#include <console.h>
|
|
|
|
#include <io.h>
|
|
|
|
#include <device/device.h>
|
|
#include <device/pci.h>
|
|
#include "mcp55.h"
|
|
|
|
static u32 final_reg;
|
|
|
|
static struct device *find_lpc_dev( struct device *dev, unsigned devfn)
|
|
{
|
|
|
|
struct device *lpc_dev;
|
|
|
|
lpc_dev = dev_find_slot(dev->bus->secondary, devfn);
|
|
|
|
if ( !lpc_dev ) return lpc_dev;
|
|
/* it had better be a PCI device */
|
|
if ( lpc_dev->id.type != DEVICE_ID_PCI)
|
|
return lpc_dev;
|
|
/* the range makes it hard to use the library function. Sorry.
|
|
* I realize this is not pretty. It would be nice if we could
|
|
* use anonymous unions.
|
|
* We now use anonymous unions. Fix up the code?
|
|
*/
|
|
if ((lpc_dev->id.pci.vendor != PCI_VENDOR_ID_NVIDIA) || (
|
|
(lpc_dev->id.pci.device < PCI_DEVICE_ID_NVIDIA_MCP55_LPC) ||
|
|
(lpc_dev->id.pci.device > PCI_DEVICE_ID_NVIDIA_MCP55_PRO)
|
|
) ) {
|
|
u32 id;
|
|
id = pci_read_config32(lpc_dev, PCI_VENDOR_ID);
|
|
if ( (id < (PCI_VENDOR_ID_NVIDIA | (PCI_DEVICE_ID_NVIDIA_MCP55_LPC << 16))) ||
|
|
(id > (PCI_VENDOR_ID_NVIDIA | (PCI_DEVICE_ID_NVIDIA_MCP55_PRO << 16)))
|
|
) {
|
|
lpc_dev = 0;
|
|
}
|
|
}
|
|
|
|
return lpc_dev;
|
|
}
|
|
|
|
static void mcp55_enable(struct device *dev)
|
|
{
|
|
struct device *lpc_dev = 0;
|
|
struct device *sm_dev = 0;
|
|
unsigned index = 0;
|
|
unsigned index2 = 0;
|
|
u32 reg_old, reg;
|
|
u8 byte;
|
|
unsigned deviceid;
|
|
unsigned vendorid;
|
|
|
|
struct southbridge_nvidia_mcp55_config *conf;
|
|
conf = dev->device_configuration;
|
|
int i;
|
|
|
|
unsigned devfn;
|
|
|
|
/* sorry. Again, anonymous unions etc. would make this easier. */
|
|
if(dev->id.pci.device==0x0000) {
|
|
vendorid = pci_read_config32(dev, PCI_VENDOR_ID);
|
|
deviceid = (vendorid>>16) & 0xffff;
|
|
// vendorid &= 0xffff;
|
|
} else {
|
|
// vendorid = dev->vendor;
|
|
deviceid = dev->id.pci.device;
|
|
}
|
|
|
|
devfn = (dev->path.pci.devfn) & ~7;
|
|
switch(deviceid) {
|
|
case PCI_DEVICE_ID_NVIDIA_MCP55_HT:
|
|
return;
|
|
|
|
case PCI_DEVICE_ID_NVIDIA_MCP55_SM2://?
|
|
index = 16;
|
|
break;
|
|
case PCI_DEVICE_ID_NVIDIA_MCP55_USB:
|
|
devfn -= (1<<3);
|
|
index = 8;
|
|
break;
|
|
case PCI_DEVICE_ID_NVIDIA_MCP55_USB2:
|
|
devfn -= (1<<3);
|
|
index = 20;
|
|
break;
|
|
case PCI_DEVICE_ID_NVIDIA_MCP55_NIC: //two
|
|
case PCI_DEVICE_ID_NVIDIA_MCP55_NIC_BRIDGE://two
|
|
devfn -= (7<<3);
|
|
index = 10;
|
|
for(i=0;i<2;i++) {
|
|
lpc_dev = find_lpc_dev(dev, devfn - (i<<3));
|
|
if(!lpc_dev) continue;
|
|
index -= i;
|
|
devfn -= (i<<3);
|
|
break;
|
|
}
|
|
break;
|
|
case PCI_DEVICE_ID_NVIDIA_MCP55_AZA:
|
|
devfn -= (5<<3);
|
|
index = 11;
|
|
break;
|
|
case PCI_DEVICE_ID_NVIDIA_MCP55_IDE:
|
|
devfn -= (3<<3);
|
|
index = 14;
|
|
break;
|
|
case PCI_DEVICE_ID_NVIDIA_MCP55_SATA0: //three
|
|
case PCI_DEVICE_ID_NVIDIA_MCP55_SATA1: //three
|
|
devfn -= (4<<3);
|
|
index = 22;
|
|
i = (dev->path.pci.devfn) & 7;
|
|
if(i>0) {
|
|
index -= (i+3);
|
|
}
|
|
break;
|
|
case PCI_DEVICE_ID_NVIDIA_MCP55_PCI:
|
|
devfn -= (5<<3);
|
|
index = 15;
|
|
break;
|
|
case PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_A:
|
|
devfn -= (0x9<<3); // to LPC
|
|
index2 = 9;
|
|
break;
|
|
case PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_B_C: //two
|
|
devfn -= (0xa<<3); // to LPC
|
|
index2 = 8;
|
|
for(i=0;i<2;i++) {
|
|
lpc_dev = find_lpc_dev(dev, devfn - (i<<3));
|
|
if(!lpc_dev) continue;
|
|
index2 -= i;
|
|
devfn -= (i<<3);
|
|
break;
|
|
}
|
|
break;
|
|
case PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_D:
|
|
devfn -= (0xc<<3); // to LPC
|
|
index2 = 6;
|
|
break;
|
|
case PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_E:
|
|
devfn -= (0xd<<3); // to LPC
|
|
index2 = 5;
|
|
break;
|
|
case PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_F:
|
|
devfn -= (0xe<<3); // to LPC
|
|
index2 = 4;
|
|
break;
|
|
default:
|
|
index = 0;
|
|
}
|
|
|
|
if(!lpc_dev)
|
|
lpc_dev = find_lpc_dev(dev, devfn);
|
|
|
|
if ( !lpc_dev ) return;
|
|
|
|
if(index2!=0) {
|
|
sm_dev = dev_find_slot(dev->bus->secondary, devfn + 1);
|
|
if(!sm_dev) return;
|
|
|
|
if ( sm_dev ) {
|
|
reg_old = reg = pci_read_config32(sm_dev, 0xe4);
|
|
|
|
if (!dev->enabled) { //disable it
|
|
reg |= (1<<index2);
|
|
}
|
|
|
|
if (reg != reg_old) {
|
|
pci_write_config32(sm_dev, 0xe4, reg);
|
|
}
|
|
}
|
|
|
|
index2 = 0;
|
|
return;
|
|
}
|
|
|
|
|
|
if ( index == 0) { // for LPC
|
|
|
|
// expose ioapic base
|
|
byte = pci_read_config8(lpc_dev, 0x74);
|
|
byte |= ((1<<1)); // expose the BAR
|
|
pci_write_config8(dev, 0x74, byte);
|
|
|
|
// expose trap base
|
|
byte = pci_read_config8(lpc_dev, 0xdd);
|
|
byte |= ((1<<0)|(1<<3)); // expose the BAR and enable write
|
|
pci_write_config8(dev, 0xdd, byte);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
if( index == 16) {
|
|
sm_dev = dev_find_slot(dev->bus->secondary, devfn + 1);
|
|
if(!sm_dev) return;
|
|
|
|
final_reg = pci_read_config32(sm_dev, 0xe8);
|
|
final_reg &= ~((1<<16)|(1<<8)|(1<<20)|(1<<14)|(1<<22)|(1<<18)|(1<<17)|(1<<15)|(1<<11)|(1<<10)|(1<<9));
|
|
pci_write_config32(sm_dev, 0xe8, final_reg); //enable all at first
|
|
#if 0
|
|
reg_old = reg = pci_read_config32(sm_dev, 0xe4);
|
|
// reg |= (1<<0);
|
|
reg &= ~(0x3f<<4);
|
|
if (reg != reg_old) {
|
|
printk(BIOS_DEBUG,"mcp55.c pcie enabled\n");
|
|
pci_write_config32(sm_dev, 0xe4, reg);
|
|
}
|
|
#endif
|
|
}
|
|
|
|
if (!dev->enabled) {
|
|
final_reg |= (1 << index);// disable it
|
|
//The reason for using final_reg, if diable func 1, the func 2 will be func 1 so We need disable them one time.
|
|
}
|
|
|
|
if(index == 9 ) { //NIC1 is the final, We need update final reg to 0xe8
|
|
sm_dev = dev_find_slot(dev->bus->secondary, devfn + 1);
|
|
if(!sm_dev) return;
|
|
reg_old = pci_read_config32(sm_dev, 0xe8);
|
|
if (final_reg != reg_old) {
|
|
pci_write_config32(sm_dev, 0xe8, final_reg);
|
|
}
|
|
|
|
}
|
|
|
|
|
|
}
|
|
|
|
void mcp55_pci_dev_set_subsystem(struct device *dev, u16 vendor, u16 device)
|
|
{
|
|
pci_write_config32(dev, PCI_MCP55_SUBSYSTEM_VENDOR_ID,
|
|
((device & 0xffff) << 16) | (vendor & 0xffff));
|
|
}
|
|
|
|
/** MCP55 specific device operation for PCI devices. */
|
|
struct pci_operations mcp55_pci_dev_ops_pci = {
|
|
.set_subsystem = mcp55_pci_dev_set_subsystem,
|
|
};
|
|
|
|
struct device_operations nvidia_ops = {
|
|
.id = {.type = DEVICE_ID_PCI,
|
|
{.pci = {.vendor = PCI_VENDOR_ID_NVIDIA,
|
|
.device = PCI_DEVICE_ID_NVIDIA_MCP55_PCI}}},
|
|
.constructor = default_device_constructor,
|
|
.phase3_scan = scan_static_bus,
|
|
.phase4_read_resources = pci_dev_read_resources,
|
|
.phase4_set_resources = pci_set_resources,
|
|
.phase5_enable_resources = mcp55_enable,
|
|
.phase6_init = NULL,
|
|
};
|
|
|
|
|