switch-coreboot/southbridge/nvidia/mcp55/lpc.dts
Ronald G. Minnich bfc217a8ce This is the current state of my mcp55 commits. I realize I overload
the system a bit so I am going to let this one get acked and I won't 
push
any more patches until this goes through. 

Add lpc support. 

Make things compile lpc.

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>

And also: 
That code is really buggy. I wonder how/if it ever worked in v2. If you
address the comments below, this is
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>

Comments (mostly) addressed. That said, I don't change functional code 
that I know works -- we can fix that later. The ops_pci is addressed by 
Carl-Daniel's patch. 


git-svn-id: svn://coreboot.org/repository/coreboot-v3@756 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-13 15:41:04 +00:00

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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-8 Ronald G. Minnich <rminnich@gmail.com> *
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
{
device_operations = "mcp55_lpc";
};