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https://github.com/fail0verflow/switch-coreboot.git
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72c2e85313
pci_set_resources. There is no matching pci_bus_set_resources, so it's confusing to see the dev function in the bus structures. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://coreboot.org/repository/coreboot-v3@1048 f3766cd6-281f-0410-b1cd-43a5c92072e9
85 lines
2.5 KiB
C
85 lines
2.5 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2004 Tyan Computer
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* Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer.
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* Copyright (C) 2006,2007 AMD
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* Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <types.h>
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#include <lib.h>
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#include <console.h>
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#include <device/pci.h>
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#include <msr.h>
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#include <legacy.h>
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#include <device/pci_ids.h>
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#include <statictree.h>
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#include <config.h>
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#include "mcp55.h"
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static void ide_init(struct device *dev)
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{
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struct southbridge_nvidia_mcp55_ide_config *conf =
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(struct southbridge_nvidia_mcp55_ide_config *)dev->device_configuration;
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/* Enable ide devices so the linux ide driver will work */
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u32 dword;
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u16 word;
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u8 byte;
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word = pci_read_config16(dev, 0x50);
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/* Ensure prefetch is disabled */
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word &= ~((1 << 15) | (1 << 13));
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if (conf->ide1_enable) {
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word |= (1<<0);
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printk(BIOS_DEBUG, "Enable secondary ide interface\t");
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}
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if (conf->ide0_enable) {
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word |= (1<<1);
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printk(BIOS_DEBUG, "Enable primary ide interfac\n");
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}
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word |= (1<<12);
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word |= (1<<14);
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pci_write_config16(dev, 0x50, word);
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byte = 0x20 ; // Latency: 64-->32
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pci_write_config8(dev, PCI_LATENCY_TIMER, byte);
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dword = pci_read_config32(dev, 0xf8);
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dword |= 12;
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pci_write_config32(dev, 0xf8, dword);
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#ifdef CONFIG_PCI_ROM_RUN
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pci_dev_init(dev);
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#endif
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}
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struct device_operations mcp55_ide = {
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.id = {.type = DEVICE_ID_PCI,
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{.pci = {.vendor = PCI_VENDOR_ID_NVIDIA,
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.device = PCI_DEVICE_ID_NVIDIA_MCP55_IDE}}},
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.constructor = default_device_constructor,
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.phase3_scan = 0,
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.phase4_read_resources = pci_dev_read_resources,
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.phase4_set_resources = pci_set_resources,
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.phase5_enable_resources = pci_dev_enable_resources,
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.phase6_init = ide_init,
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.ops_pci = &mcp55_pci_dev_ops_pci,
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};
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