mirror of
https://github.com/fail0verflow/switch-coreboot.git
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539a101e1b
hardware and have a specific size. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://coreboot.org/repository/coreboot-v3@1069 f3766cd6-281f-0410-b1cd-43a5c92072e9
87 lines
2.6 KiB
C
87 lines
2.6 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008 coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <types.h>
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#include <lib.h>
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#include <console.h>
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#include <device/pci.h>
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#include <msr.h>
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#include <legacy.h>
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#include <device/pci_ids.h>
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#include <statictree.h>
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#include <config.h>
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#include "i82801gx.h"
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static void usb_ehci_init(struct device *dev)
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{
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u32 reg32;
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printk(BIOS_DEBUG, "EHCI: Setting up controller.. ");
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reg32 = pci_read_config32(dev, PCI_COMMAND);
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pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER);
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reg32 = pci_read_config32(dev, 0xdc);
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reg32 |= (1 << 31) | (1 << 27);
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pci_write_config32(dev, 0xdc, reg32);
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reg32 = pci_read_config32(dev, 0xfc);
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reg32 &= ~(3 << 2);
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reg32 |= (2 << 2) | (1 << 29) | (1 << 17);
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pci_write_config32(dev, 0xfc, reg32);
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printk(BIOS_DEBUG, "done.\n");
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}
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static void usb_ehci_set_subsystem(struct device * dev, u16 vendor, u16 device)
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{
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u8 access_cntl;
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access_cntl = pci_read_config8(dev, 0x80);
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/* Enable writes to protected registers. */
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pci_write_config8(dev, 0x80, access_cntl | 1);
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/* Write the subsystem vendor and device ID. */
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pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
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((device & 0xffff) << 16) | (vendor & 0xffff));
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/* Restore protection. */
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pci_write_config8(dev, 0x80, access_cntl);
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}
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static struct pci_operations lops_pci = {
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.set_subsystem = &usb_ehci_set_subsystem,
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};
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/* 82801GB/GR/GDH/GBM/GHM/GU (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH/ICH7-U) */
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void i82801gx_enable(struct device * dev);
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struct device_operations i82801gx_usb_ehci = {
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.id = {.type = DEVICE_ID_PCI,
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{.pci = {.vendor = PCI_VENDOR_ID_INTEL,
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.device = 0x27cc}}},
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.constructor = default_device_constructor,
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.phase3_chip_setup_dev = i82801gx_enable,
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.phase4_read_resources = pci_dev_read_resources,
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.phase4_set_resources = pci_set_resources,
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.phase5_enable_resources = pci_bus_enable_resources,
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.phase6_init = usb_ehci_init,
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.ops_pci = &lops_pci,
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};
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