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d7e12d6d07
This is from v2. Once again, the pattern: - save the chip name for the common enable parts, hence i82801gx.c - remove the leading i82801_ from most other bits, since we compile in different directories now - Every device of a type has a distinct .c file (e.g. pcie.c) - Each device of a type may be realized in more than one bit of silicon, and have more than one set of operations, although code is common. These are placed into distinct operations structs (see pcie.c) - for every distinct device, there is a .dts file. This set of rules makes for simple cross-part standardization of code. Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://coreboot.org/repository/coreboot-v3@991 f3766cd6-281f-0410-b1cd-43a5c92072e9
35 lines
925 B
Text
35 lines
925 B
Text
Non-automatic IO-Addresses
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The following dynamic IO BARs are used on the ICH7 for the Kontron Default BIOS:
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GPIOBASE 0x480 (64 bytes)
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PMBASE 0x800 (128 bytes)
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SMBASE 0x400 (32 bytes)
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HWMON 0xa00 (??)
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The following dynamic IO BARs are used on the ICH7 for the Getac Default BIOS:
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GPIOBASE 0x1180 (64 bytes)
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PMBASE 0x1000 (128 bytes)
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SMBASE 0x18e0 (32 bytes)
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The Getac also needs an IO Trapped area of 0x0C bytes (defaults to 0x800)
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coreboot:
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GPIOBASE 0x480 (64 bytes)
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PMBASE 0x500 (128 bytes)
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SMBASE 0x400 (32 bytes)
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HWMON 0xa00 (??)
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NOTE: Coreboot sets the SMBASE to 0xf00 in auto.c. But it gets relocated
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in stage2 because its a "normal BAR" (to 0x2080 in one case here).
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This is not unhealthy but at least confusing. We should provide a method to
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nail down certain resources for stage2.
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For a list of static I/O space allocation look at 6.3.1 of the ICH7 Family
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Datasheet.
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