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https://github.com/fail0verflow/switch-coreboot.git
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267ce7cbf7
file-by-file changes: dts: There are no bus devices, remove it. Add the northbridge devices. Fix susbsytem_vendor and subsystem_device. southbridge/intel/i82371eb/ide: Make the ide enabled by default. northbridge/intel/i440bxemulation/i440bx.c: 1. Split ops into domain and northbridge A. Domain should have bus ops, scan_bus, etc. B. Northbridge should have ops for its own registers. In this case it only needs read and set resources. functions: i440bx_read_resources - set up the IO and VGA resources. VGA is fixed. i440bx_ram_resources - this should be called after resource assignment. i440bx_set_resources - call pci_set_resources then i440bx_ram_resources. i440bx_domain_read_resources - Set up system-wide resources, and reserve space for the local APIC. I put the IOAPIC here too, but it belongs somewhere in the southbridge. i440bx_domain_set_resources - Mark the domain-specific resources as stored (In a real device you'd probably need to set some registers here.) Call phase4_set_resources for children. southbridge/intel/i82371eb/i82371eb.c: 1. Add ISA read and set resources to reserve legacy IO space. - Note that since it's subtractively decoded, it doesn't need to be stored anywhere. It needs to be marked stored so pci_set_resource doesn't try to store it. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://coreboot.org/repository/coreboot-v3@1092 f3766cd6-281f-0410-b1cd-43a5c92072e9 |
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| acpi | ||
| i82371eb.c | ||
| ide | ||
| isa | ||
| Makefile | ||