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https://github.com/fail0verflow/switch-coreboot.git
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72c2e85313
pci_set_resources. There is no matching pci_bus_set_resources, so it's confusing to see the dev function in the bus structures. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://coreboot.org/repository/coreboot-v3@1048 f3766cd6-281f-0410-b1cd-43a5c92072e9
95 lines
2.8 KiB
C
95 lines
2.8 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <types.h>
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#include <lib.h>
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#include <console.h>
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#include <device/pci.h>
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#include <msr.h>
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#include <legacy.h>
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#include <device/pci_ids.h>
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#include <statictree.h>
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#include <config.h>
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#include "rs690.h"
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/* for UMA internal graphics */
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void avoid_lpc_dma_deadlock(struct device * nb_dev, struct device * sb_dev)
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{
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struct device * k8_f0;
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u8 reg;
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k8_f0 = dev_find_slot(0, PCI_DEVFN(0x18, 0));
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set_nbcfg_enable_bits(k8_f0, 0x68, 3 << 21, 1 << 21);
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reg = nbpcie_p_read_index(sb_dev, 0x10);
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reg |= 0x100; /* bit9=1 */
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nbpcie_p_write_index(sb_dev, 0x10, reg);
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reg = nbpcie_p_read_index(nb_dev, 0x10);
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reg |= 0x100; /* bit9=1 */
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nbpcie_p_write_index(nb_dev, 0x10, reg);
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/* Enable NP protocol over PCIE for memory-mapped writes targeting LPC
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* Set this bit to avoid a deadlock condition. */
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reg = htiu_read_index(nb_dev, 0x6);
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reg |= 0x1000000; /* bit26 */
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htiu_write_index(nb_dev, 0x6, reg);
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}
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static void pcie_init(struct device *dev)
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{
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/* Enable pci error detecting */
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u32 dword;
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printk(BIOS_INFO, "pcie_init in rs690_ht.c\n");
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/* System error enable */
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dword = pci_read_config32(dev, PCI_COMMAND);
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dword |= (1 << 8); /* System error enable */
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dword |= (1 << 30); /* Clear possible errors */
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pci_write_config32(dev, PCI_COMMAND, dword);
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/*
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* 1 is APIC enable
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* 18 is enable nb to accept A4 interrupt request from SB.
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*/
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dword = pci_read_config32(dev, 0x4C);
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dword |= 1 << 1 | 1 << 18; /* Clear possible errors */
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pci_write_config32(dev, 0x4C, dword);
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}
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static struct pci_operations lops_pci = {
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.set_subsystem = pci_dev_set_subsystem,
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};
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void rs690_enable(struct device * dev);
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struct device_operations rs690_ht = {
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.id = {.type = DEVICE_ID_PCI,
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{.pci = {.vendor = PCI_VENDOR_ID_ATI,
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.device = PCI_DEVICE_ID_ATI_RS690_HT}}},
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.constructor = default_device_constructor,
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.phase3_scan = 0,
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.phase3_chip_setup_dev = rs690_enable,
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.phase4_read_resources = pci_dev_read_resources,
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.phase4_set_resources = pci_set_resources,
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.phase5_enable_resources = pci_dev_enable_resources,
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.phase6_init = pcie_init,
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.ops_pci = &lops_pci,
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};
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