mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
cedf16ca69
cleanups/fixes. Fixup device tree code. Add/change methods as needed. This should help serengeti. Signed-off-by: Ronald G. Minnich<rminnich@gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Corey Osgood <corey.osgood@gmail.com> Acked-by: Marc Jones <marc.jones@amd.com> git-svn-id: svn://coreboot.org/repository/coreboot-v3@954 f3766cd6-281f-0410-b1cd-43a5c92072e9
44 lines
2 KiB
Text
44 lines
2 KiB
Text
/*
|
|
* This file is part of the coreboot project.
|
|
*
|
|
* Copyright (C) 2008 Ronald G. Minnich <rminnich@gmail.com>
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify
|
|
* it under the terms of the GNU General Public License as published by
|
|
* the Free Software Foundation; either version 2 of the License, or
|
|
* (at your option) any later version.
|
|
*
|
|
* This program is distributed in the hope that it will be useful,
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
* GNU General Public License for more details.
|
|
*
|
|
* You should have received a copy of the GNU General Public License
|
|
* along with this program; if not, write to the Free Software
|
|
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
|
*/
|
|
|
|
/*
|
|
#Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default)
|
|
#Define vga_rom_address = 0xfff0000
|
|
#Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7)
|
|
#Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3,
|
|
# 1: the system allows a PCIE link to be established on Dev2 or Dev3.
|
|
#Define gfx_dual_slot, 0: single slot, 1: dual slot
|
|
#Define gfx_lane_reversal, 0: disable lane reversal, 1: enable
|
|
#Define gfx_tmds, 0: didn't support TMDS, 1: support
|
|
#Define gfx_compliance, 0: didn't support compliance, 1: support
|
|
#Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration
|
|
#Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16
|
|
*/
|
|
{
|
|
device_operations = "rs690_gfx";
|
|
vga_rom_address = "0xfff0000";
|
|
gfx_dev2_dev3 = "1"; /* for GFX Core initialization REFCLK_SEL */
|
|
gfx_dual_slot = "0"; /* Is it dual graphics slots */
|
|
gfx_lane_reversal = "0"; /* Single/Dual slot lan reversal */
|
|
gfx_tmds = "0"; /* whether support TMDS? */
|
|
gfx_compliance = "0"; /* whether support compliance? */
|
|
gfx_reconfiguration = "1"; /* Dynamic Lind Width Control */
|
|
gfx_link_width = "0"; /* Desired width of lane 2 */
|
|
};
|