mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
b1dfc9858a
23K, too large. dbe62 was tested and works i.e. this does no harm. Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://coreboot.org/repository/coreboot-v3@893 f3766cd6-281f-0410-b1cd-43a5c92072e9
33 lines
1.2 KiB
Makefile
33 lines
1.2 KiB
Makefile
##
|
|
## This file is part of the coreboot project.
|
|
##
|
|
## Copyright (C) 2007 coresystems GmbH
|
|
## (Written by Stefan Reinauer <stepan@coresystems.de> for coresystems GmbH)
|
|
##
|
|
## This program is free software; you can redistribute it and/or modify
|
|
## it under the terms of the GNU General Public License as published by
|
|
## the Free Software Foundation; either version 2 of the License, or
|
|
## (at your option) any later version.
|
|
##
|
|
## This program is distributed in the hope that it will be useful,
|
|
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
## GNU General Public License for more details.
|
|
##
|
|
## You should have received a copy of the GNU General Public License
|
|
## along with this program; if not, write to the Free Software
|
|
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
|
##
|
|
|
|
ifeq ($(CONFIG_SOUTHBRIDGE_AMD_RS690),y)
|
|
|
|
STAGE2_CHIPSET_SRC += $(src)/southbridge/amd/rs690/cmn.c \
|
|
$(src)/southbridge/amd/rs690/gfx.c \
|
|
$(src)/southbridge/amd/rs690/ht.c \
|
|
$(src)/southbridge/amd/rs690/pcie.c \
|
|
$(src)/southbridge/amd/rs690/rs690.c
|
|
|
|
STAGE0_CHIPSET_SRC += $(src)/southbridge/amd/rs690/stage1.c
|
|
|
|
|
|
endif
|