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https://github.com/fail0verflow/switch-coreboot.git
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3169211c8b
Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://coreboot.org/repository/coreboot-v3@1080 f3766cd6-281f-0410-b1cd-43a5c92072e9
88 lines
2.6 KiB
C
88 lines
2.6 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2003 Yinghai Lu, Tyan
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <types.h>
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#include <lib.h>
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#include <console.h>
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#include <device/pci.h>
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#include <msr.h>
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#include <legacy.h>
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#include <device/pci_ids.h>
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#include <statictree.h>
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#include <config.h>
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static void agp3bridge_init(struct device * dev)
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{
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u8 byte;
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/* Enable BM, MEM and IO */
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/* this config32 is arguably wrong but I won't change until we can test. */
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byte = pci_read_config32(dev, PCI_COMMAND);
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byte |= 0x07;
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pci_write_config8(dev, PCI_COMMAND, byte);
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return;
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}
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struct device_operations amd8151_agp3bridge = {
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.id = {.type = DEVICE_ID_PCI,
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{.pci = {.vendor = PCI_VENDOR_ID_AMD,
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.device = PCI_DEVICE_ID_AMD_8151_AGP}}},
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.constructor = default_device_constructor,
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.phase3_scan = pci_scan_bridge,
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.phase4_read_resources = pci_bus_read_resources,
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.phase4_set_resources = pci_set_resources,
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.phase5_enable_resources = pci_bus_enable_resources,
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.phase6_init = agp3bridge_init,
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};
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static void agp3dev_enable(struct device * dev)
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{
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u32 value;
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/* AGP enable */
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value = pci_read_config32(dev, 0xa8);
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value |= (3<<8)|2; //AGP 8x
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pci_write_config32(dev, 0xa8, value);
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/* enable BM and MEM */
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value = pci_read_config32(dev, PCI_COMMAND);
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value |= 6;
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pci_write_config32(dev, PCI_COMMAND, value);
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#if 0
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/* FIXME: should we add agp aperture base and size here ?
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* or it is done by AGP drivers */
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#endif
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}
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static struct pci_operations pci_ops_pci_dev = {
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.set_subsystem = pci_dev_set_subsystem,
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};
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struct device_operations amd8151_agp3dev = {
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.id = {.type = DEVICE_ID_PCI,
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{.pci = {.vendor = PCI_VENDOR_ID_AMD,
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.device = PCI_DEVICE_ID_AMD_8151_SYSCTRL}}},
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.constructor = default_device_constructor,
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.phase3_enable = agp3dev_enable,
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.phase4_read_resources = pci_dev_read_resources,
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.phase4_set_resources = pci_set_resources,
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.phase5_enable_resources = pci_dev_enable_resources,
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.phase6_init = NULL,
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.ops_pci = &pci_dev_ops_pci,
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};
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