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https://github.com/fail0verflow/switch-coreboot.git
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539a101e1b
hardware and have a specific size. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://coreboot.org/repository/coreboot-v3@1069 f3766cd6-281f-0410-b1cd-43a5c92072e9
109 lines
2.9 KiB
C
109 lines
2.9 KiB
C
/*
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*
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* This file is part of the coreboot project.
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* Copyright (C) 2003 Linux Networx
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* Copyright (C) 2008 Ronald G. Minnich <rminnich@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
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*/
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#include <types.h>
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#include <lib.h>
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#include <console.h>
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#include <device/pci.h>
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#include <msr.h>
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#include <legacy.h>
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#include <device/pci_ids.h>
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#include <statictree.h>
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#include <config.h>
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#include "amd8111.h"
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#define CMD3 0x54
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typedef enum {
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VAL3 = (1 << 31), /* VAL bit for byte 3 */
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VAL2 = (1 << 23), /* VAL bit for byte 2 */
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VAL1 = (1 << 15), /* VAL bit for byte 1 */
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VAL0 = (1 << 7), /* VAL bit for byte 0 */
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}VAL_BITS;
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typedef enum {
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/* VAL3 */
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ASF_INIT_DONE_ALIAS = (1 << 29),
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/* VAL2 */
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JUMBO = (1 << 21),
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VSIZE = (1 << 20),
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VLONLY = (1 << 19),
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VL_TAG_DEL = (1 << 18),
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/* VAL1 */
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EN_PMGR = (1 << 14),
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INTLEVEL = (1 << 13),
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FORCE_FULL_DUPLEX = (1 << 12),
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FORCE_LINK_STATUS = (1 << 11),
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APEP = (1 << 10),
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MPPLBA = (1 << 9),
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/* VAL0 */
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RESET_PHY_PULSE = (1 << 2),
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RESET_PHY = (1 << 1),
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PHY_RST_POL = (1 << 0),
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}CMD3_BITS;
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static void nic_init(struct device *dev)
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{
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struct southbridge_amd_amd8111_nic_config *conf;
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struct resource *resource;
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unsigned long mmio;
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conf = dev->device_configuration;
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resource = find_resource(dev, PCI_BASE_ADDRESS_0);
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mmio = resource->base;
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/* Hard Reset PHY */
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printk(BIOS_DEBUG, "Reseting PHY... ");
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/*
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if (conf->phy_lowreset) {
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writel(VAL0 | PHY_RST_POL | RESET_PHY , (void *)(mmio + CMD3));
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} else {
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writel(VAL0 | RESET_PHY, (void *)(mmio + CMD3));
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}
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mdelay(15);
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writel(RESET_PHY, (void *)(mmio + CMD3));
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*/
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printk(BIOS_DEBUG, "Done\n");
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}
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static void lpci_set_subsystem(struct device * dev, u16 vendor, u16 device)
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{
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pci_write_config32(dev, 0xc8,
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((device & 0xffff) << 16) | (vendor & 0xffff));
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}
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static struct pci_operations lops_pci = {
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.set_subsystem = lpci_set_subsystem,
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};
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struct device_operations amd8111_nic = {
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.id = {.type = DEVICE_ID_PCI,
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{.pci = {.vendor = PCI_VENDOR_ID_AMD,
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.device = PCI_DEVICE_ID_AMD_8111_NIC}}},
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.constructor = default_device_constructor,
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.phase3_scan = 0,
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.phase3_chip_setup_dev = amd8111_enable,
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.phase4_read_resources = pci_dev_read_resources,
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.phase4_set_resources = pci_set_resources,
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.phase5_enable_resources = pci_dev_enable_resources,
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.phase6_init = nic_init,
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.ops_pci = &lops_pci,
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};
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