mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
d4480beaec
This patch makes specific devices use the updated resource allocation code.
The changes necessary are:
1. Remove all calls to compute_allocate_resources.
2. Don't store resources except in phase4_set_resources.
northbridge/amd/k8/pci.c:
Remove calls to compute_allocate_resource.
Change phase4_assign_resources to phase4_set_resources
southbridge/amd/amd8132/amd8132_bridge.c:
Remove NPUML and NPUMB.
Add a warning for bus disabling.
Remove bridge_{read|set}_resources (they were there for NPUML)
southbridge/nvidia/mcp55/lpc.c:
southbridge/amd/sb600/lpc.c:
Remove references to have_resources.
southbridge/amd/amd8111/lpc.c:
Add resources for subtractive IO and ROM.
northbridge/amd/k8/domain.c:
northbridge/intel/i440bxemulation/i440bx.c:
northbridge/amd/geodelx/geodelx.c:
northbridge/intel/i945/northbridge.c:
northbridge/via/cn700/stage2.c:
Change phase4_assign_resources->phase4_set_resources.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1090 f3766cd6-281f-0410-b1cd-43a5c92072e9
230 lines
6.2 KiB
C
230 lines
6.2 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2003 Linux NetworX, SuSE Linux AG
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* Copyright (C) 2006 AMD
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <types.h>
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#include <lib.h>
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#include <console.h>
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#include <device/pci.h>
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#include <msr.h>
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#include <legacy.h>
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#include <device/pci_ids.h>
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#include <statictree.h>
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#include <config.h>
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#include <lapic.h>
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#include <mc146818rtc.h>
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#include "amd8111.h"
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#define NMI_OFF 0
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struct ioapicreg {
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unsigned int reg;
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unsigned int value_low, value_high;
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};
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static struct ioapicreg ioapicregvalues[] = {
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#define ALL (0xff << 24)
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#define NONE (0)
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#define DISABLED (1 << 16)
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#define ENABLED (0 << 16)
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#define TRIGGER_EDGE (0 << 15)
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#define TRIGGER_LEVEL (1 << 15)
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#define POLARITY_HIGH (0 << 13)
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#define POLARITY_LOW (1 << 13)
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#define PHYSICAL_DEST (0 << 11)
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#define LOGICAL_DEST (1 << 11)
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#define ExtINT (7 << 8)
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#define NMI (4 << 8)
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#define SMI (2 << 8)
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#define INT (1 << 8)
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/* IO-APIC virtual wire mode configuration */
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/* mask, trigger, polarity, destination, delivery, vector */
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{ 0, ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | ExtINT, NONE},
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{ 1, DISABLED, NONE},
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{ 2, DISABLED, NONE},
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{ 3, DISABLED, NONE},
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{ 4, DISABLED, NONE},
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{ 5, DISABLED, NONE},
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{ 6, DISABLED, NONE},
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{ 7, DISABLED, NONE},
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{ 8, DISABLED, NONE},
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{ 9, DISABLED, NONE},
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{ 10, DISABLED, NONE},
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{ 11, DISABLED, NONE},
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{ 12, DISABLED, NONE},
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{ 13, DISABLED, NONE},
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{ 14, DISABLED, NONE},
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{ 15, DISABLED, NONE},
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{ 16, DISABLED, NONE},
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{ 17, DISABLED, NONE},
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{ 18, DISABLED, NONE},
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{ 19, DISABLED, NONE},
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{ 20, DISABLED, NONE},
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{ 21, DISABLED, NONE},
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{ 22, DISABLED, NONE},
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{ 23, DISABLED, NONE},
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/* Be careful and don't write past the end... */
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};
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static void setup_ioapic(void)
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{
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int i;
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unsigned long value_low, value_high;
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unsigned long ioapic_base = 0xfec00000;
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volatile unsigned long *l;
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struct ioapicreg *a = ioapicregvalues;
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unsigned long bsp_apicid = lapicid();
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l = (unsigned long *) ioapic_base;
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ioapicregvalues[0].value_high = bsp_apicid<<(56-32);
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printk(BIOS_DEBUG, "amd8111: ioapic bsp_apicid = %02lx\n", bsp_apicid);
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for (i = 0; i < ARRAY_SIZE(ioapicregvalues);
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i++, a++) {
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l[0] = (a->reg * 2) + 0x10;
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l[4] = a->value_low;
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value_low = l[4];
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l[0] = (a->reg *2) + 0x11;
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l[4] = a->value_high;
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value_high = l[4];
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if ((i==0) && (value_low == 0xffffffff)) {
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printk(BIOS_WARNING, "IO APIC not responding.\n");
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return;
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}
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printk(BIOS_SPEW, "for IRQ, reg 0x%08x value 0x%08x 0x%08x\n",
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a->reg, a->value_low, a->value_high);
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}
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}
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static void enable_hpet(struct device *dev)
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{
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unsigned long hpet_address;
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pci_write_config32(dev,0xa0, 0xfed00001);
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hpet_address = pci_read_config32(dev,0xa0)& 0xfffffffe;
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printk(BIOS_DEBUG, "enabling HPET @0x%lx\n", hpet_address);
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}
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static void lpc_init(struct device *dev)
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{
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u8 byte;
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int nmi_option;
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/* IO APIC initialization */
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byte = pci_read_config8(dev, 0x4B);
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byte |= 1;
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pci_write_config8(dev, 0x4B, byte);
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setup_ioapic();
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/* posted memory write enable */
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byte = pci_read_config8(dev, 0x46);
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pci_write_config8(dev, 0x46, byte | (1<<0));
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/* Enable 5Mib Rom window */
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byte = pci_read_config8(dev, 0x43);
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byte |= 0xc0;
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pci_write_config8(dev, 0x43, byte);
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/* Enable Port 92 fast reset */
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byte = pci_read_config8(dev, 0x41);
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byte |= (1 << 5);
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pci_write_config8(dev, 0x41, byte);
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/* Enable Error reporting */
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/* Set up sync flood detected */
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byte = pci_read_config8(dev, 0x47);
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byte |= (1 << 1);
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pci_write_config8(dev, 0x47, byte);
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/* Set up NMI on errors */
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byte = pci_read_config8(dev, 0x40);
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byte |= (1 << 1); /* clear PW2LPC error */
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byte |= (1 << 6); /* clear LPCERR */
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pci_write_config8(dev, 0x40, byte);
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nmi_option = NMI_OFF;
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get_option(&nmi_option, "nmi");
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if (nmi_option) {
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byte |= (1 << 7); /* set NMI */
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pci_write_config8(dev, 0x40, byte);
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}
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/* Initialize the real time clock */
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rtc_init(0);
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/* Initialize isa dma */
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isa_dma_init();
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/* Initialize the High Precision Event Timers */
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enable_hpet(dev);
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}
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static void amd8111_lpc_read_resources(struct device * dev)
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{
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struct resource *res;
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/* Get the normal pci resources of this device */
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pci_dev_read_resources(dev);
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/* Add an extra subtractive resource for both memory and I/O */
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res = new_resource(dev, 0);
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res->base = 0x0;
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res->size = 0x1000;
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res->limit = 0xffff;
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res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
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IORESOURCE_ASSIGNED | IORESOURCE_FIXED | IORESOURCE_STORED;
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res = new_resource(dev, 1);
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res->base = 0xff000000UL;
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res->size = 0x01000000UL;
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res->limit = 0xffffffffUL;
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res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
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IORESOURCE_ASSIGNED | IORESOURCE_FIXED | IORESOURCE_STORED;
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}
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static void amd8111_lpc_enable_resources(struct device * dev)
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{
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pci_dev_enable_resources(dev);
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enable_childrens_resources(dev);
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}
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static void lpci_set_subsystem(struct device * dev, u16 vendor, u16 device)
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{
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pci_write_config32(dev, 0x70,
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((device & 0xffff) << 16) | (vendor & 0xffff));
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}
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static struct pci_operations lops_pci = {
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.set_subsystem = lpci_set_subsystem,
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};
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struct device_operations amd8111_lpc = {
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.id = {.type = DEVICE_ID_PCI,
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{.pci = {.vendor = PCI_VENDOR_ID_AMD,
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.device = PCI_DEVICE_ID_AMD_8111_ISA}}},
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.constructor = default_device_constructor,
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.phase3_scan = scan_static_bus,
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.phase3_chip_setup_dev = amd8111_enable,
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.phase4_read_resources = amd8111_lpc_read_resources,
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.phase4_set_resources = pci_set_resources,
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.phase5_enable_resources = amd8111_lpc_enable_resources,
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.phase6_init = lpc_init,
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.ops_pci = &lops_pci,
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};
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