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4216c13386
payload. Signed-off-by: Corey Osgood <corey.osgood@gmail.com> Acked-by: Corey Osgood <corey.osgood@gmail.com> git-svn-id: svn://coreboot.org/repository/coreboot-v3@1077 f3766cd6-281f-0410-b1cd-43a5c92072e9
93 lines
2.9 KiB
C
93 lines
2.9 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007-2008 Corey Osgood <corey.osgood@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <types.h>
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#include <lib.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <statictree.h>
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#include <config.h>
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#include "cn700.h"
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static void memctrl_init(struct device *dev)
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{
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struct device *vlink_dev;
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u16 reg16;
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u8 ranks, pagec, paged, pagee, pagef, shadowreg;
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/* Set up the VGA framebuffer size. */
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reg16 = (log2f(CONFIG_CN700_VIDEO_MB_32) << 12) | (1 << 15);
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pci_write_config16(dev, 0xa0, reg16);
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/* Set up VGA timers. */
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pci_write_config8(dev, 0xa2, 0x44);
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for (ranks = 0x4b; ranks >= 0x48; ranks--) {
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if (pci_read_config8(dev, ranks)) {
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ranks -= 0x48;
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break;
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}
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}
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if (ranks == 0x47)
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ranks = 0x00;
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reg16 = 0xaae0;
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reg16 |= ranks;
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/* GMINT Misc. FrameBuffer rank */
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pci_write_config16(dev, 0xb0, reg16);
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/* AGPCINT Misc. */
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pci_write_config8(dev, 0xb8, 0x08);
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/* TODO: This doesn't belong here. At the very least make it a dts
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* option */
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#if 0 /* Handled in stage1 */
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/* Shadow RAM */
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pagec = 0xff, paged = 0xff, pagee = 0xff, pagef = 0x30;
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/* PAGE C, D, E are all read write enable */
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pci_write_config8(dev, 0x80, pagec);
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pci_write_config8(dev, 0x81, paged);
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pci_write_config8(dev, 0x82, pagee);
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/* PAGE F are read/writable */
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shadowreg = pci_read_config8(dev, 0x83);
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shadowreg |= pagef;
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pci_write_config8(dev, 0x83, shadowreg);
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/* vlink mirror */
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vlink_dev = dev_find_slot(0, PCI_BDF(0, 7, 0))
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pci_write_config8(vlink_dev, 0x61, pagec);
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pci_write_config8(vlink_dev, 0x62, paged);
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pci_write_config8(vlink_dev, 0x64, pagee);
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shadowreg = pci_read_config8(vlink_dev, 0x63);
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shadowreg |= pagef;
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pci_write_config8(vlink_dev, 0x63, shadowreg);
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#endif
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}
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struct device_operations cn700_memctrl = {
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.id = {.type = DEVICE_ID_PCI,
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{.pci = {.vendor = PCI_VENDOR_ID_VIA,
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.device = PCI_DEVICE_ID_VIA_CN700_MEMCTRL}}},
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.constructor = default_device_constructor,
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//.phase3_scan = scan_static_bus,
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.phase4_read_resources = pci_dev_read_resources,
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.phase4_set_resources = pci_set_resources,
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.phase5_enable_resources = pci_dev_enable_resources,
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.phase6_init = memctrl_init,
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.ops_pci = &pci_dev_ops_pci,
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};
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