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267ce7cbf7
file-by-file changes: dts: There are no bus devices, remove it. Add the northbridge devices. Fix susbsytem_vendor and subsystem_device. southbridge/intel/i82371eb/ide: Make the ide enabled by default. northbridge/intel/i440bxemulation/i440bx.c: 1. Split ops into domain and northbridge A. Domain should have bus ops, scan_bus, etc. B. Northbridge should have ops for its own registers. In this case it only needs read and set resources. functions: i440bx_read_resources - set up the IO and VGA resources. VGA is fixed. i440bx_ram_resources - this should be called after resource assignment. i440bx_set_resources - call pci_set_resources then i440bx_ram_resources. i440bx_domain_read_resources - Set up system-wide resources, and reserve space for the local APIC. I put the IOAPIC here too, but it belongs somewhere in the southbridge. i440bx_domain_set_resources - Mark the domain-specific resources as stored (In a real device you'd probably need to set some registers here.) Call phase4_set_resources for children. southbridge/intel/i82371eb/i82371eb.c: 1. Add ISA read and set resources to reserve legacy IO space. - Note that since it's subtractively decoded, it doesn't need to be stored anywhere. It needs to be marked stored so pci_set_resource doesn't try to store it. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://coreboot.org/repository/coreboot-v3@1092 f3766cd6-281f-0410-b1cd-43a5c92072e9
95 lines
4 KiB
C
95 lines
4 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef NORTHBRIDGE_INTEL_I440BXEMULATION_I440BX_H
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#define NORTHBRIDGE_INTEL_I440BXEMULATION_I440BX_H
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#include <device/device.h>
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/*
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* Datasheet:
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* - Name: Intel 440BX AGPset: 82443BX Host Bridge/Controller
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* - URL: http://www.intel.com/design/chipsets/datashts/290633.htm
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* - PDF: http://www.intel.com/design/chipsets/datashts/29063301.pdf
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* - Order Number: 290633-001
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*/
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/*
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* Host-to-PCI Bridge Registers.
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* The values in parenthesis are the default values as per datasheet.
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* Any addresses between 0x00 and 0xff not listed below are either
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* Reserved or Intel Reserved and should not be touched.
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*/
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#define VID 0x00 /* Vendor Identification (0x8086). */
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#define DID 0x02 /* Device Identification (0x7190/0x7192). */
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#define PCICMD 0x04 /* PCI Command Register (0x006). */
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#define PCISTS 0x06 /* PCI Status Register (0x0210/0x0200). */
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#define RID 0x08 /* Revision Identification (0x00/0x01/0x02). */
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#define SUBC 0x0a /* Sub-Class Code (0x00). */
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#define BCC 0x0b /* Base Class Code (0x06). */
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#define MLT 0x0d /* Master Latency Timer (0x00). */
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#define HDR 0x0e /* Header Type (0x00). */
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#define APBASE 0x10 /* Aperture Base Configuration (0x00000008). */
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#define SVID 0x2c /* Subsystem Vendor Identification (0x0000). */
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#define SID 0x2e /* Subsystem Identification (0x0000). */
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#define CAPPTR 0x34 /* Capabilities Pointer (0xa0/0x00). */
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#define NBXCFG 0x50 /* 440BX Configuration (0x0000:00S0_0000_000S_0S00b). */
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#define DRAMC 0x57 /* DRAM Control (00S0_0000b). */
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#define DRAMT 0x58 /* DRAM Timing (0x03). */
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#define PAM 0x59 /* Programmable Attribute Map, 7 registers (0x00). */
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#define DRB 0x60 /* DRAM Row Boundary, 8 registers (0x01). */
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#define FDHC 0x68 /* Fixed SDRAM Hole Control (0x00). */
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#define MBSC 0x69 /* Memory Buffer Strength Control (0x0000-0000-0000). */
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#define SMRAM 0x72 /* System Management RAM Control (0x02). */
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#define ESMRAMC 0x73 /* Extended System Management RAM Control (0x38). */
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#define RPS 0x74 /* SDRAM Row Page Size (0x0000). */
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#define SDRAMC 0x76 /* SDRAM Control Register (0x0000). */
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#define PGPOL 0x78 /* Paging Policy Register (0x00). */
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#define PMCR 0x7a /* Power Management Control Register (0000_S0S0b). */
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#define SCRR 0x7b /* Suspend CBR Refresh Rate Register (0x0038). */
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#define EAP 0x80 /* Error Address Pointer Register (0x00000000). */
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#define ERRCMD 0x90 /* Error Command Register (0x80). */
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#define ERRSTS 0x91 /* Error Status (0x0000). */
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// TODO: AGP stuff.
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#define MBFS 0xca /* Memory Buffer Frequency Select (0x000000). */
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#define BSPAD 0xd0 /* BIOS Scratch Pad (0x000..000). */
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#define DWTC 0xe0 /* DRAM Write Thermal Throttling Control (0x000..000). */
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#define DRTC 0xe8 /* DRAM Read Thermal Throttling Control (0x000..000). */
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#define BUFFC 0xf0 /* Buffer Control Register (0x0000). */
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/* For convenience: */
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#define DRB0 0x60
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#define DRB1 0x61
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#define DRB2 0x62
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#define DRB3 0x63
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#define DRB4 0x64
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#define DRB5 0x65
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#define DRB6 0x66
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#define DRB7 0x67
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#define PAM0 0x59
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#define PAM1 0x5a
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#define PAM2 0x5b
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#define PAM3 0x5c
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#define PAM4 0x5d
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#define PAM5 0x5e
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#define PAM6 0x5f
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#endif /* NORTHBRIDGE_INTEL_I440BXEMULATION_I440BX_H */
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