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https://github.com/fail0verflow/switch-coreboot.git
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cb5d9d3867
The device infrastructure already has an enabled bit, so we don't need to duplicate it in the current form. cs5536.c:ide_init() is phase6_init, which is called only if the device is enabled, so if the device doesn't exist, or the mainboard dts says "disabled;" for it, the init is not done and an extra conditional is not necessary. Adapt all cs5536 using mainboards to it (removing enable_ide variable) - artecgroup/dbe6[12] gets the whole IDE device removed, which results in the ide_init() code not being ran as before (before it was called but early return from enable_ide == 0, now it won't be called in the first place). Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://coreboot.org/repository/coreboot-v3@1114 f3766cd6-281f-0410-b1cd-43a5c92072e9
63 lines
1.9 KiB
Text
63 lines
1.9 KiB
Text
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007 Ronald G. Minnich <rminnich@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/{
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mainboard_vendor = "AMD";
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mainboard_name = "DB800";
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mainboard_pci_subsystem_vendor = "0x1022";
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mainboard_pci_subsystem_device = "0x2323";
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cpus { };
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apic@0 {
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/config/("northbridge/amd/geodelx/apic");
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};
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domain@0 {
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/config/("northbridge/amd/geodelx/domain");
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pci@1,0 {
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/config/("northbridge/amd/geodelx/pci");
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/* Video RAM has to be in 2MB chunks. */
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geode_video_mb = "8";
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};
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pci@1,1 { /* Graphics */
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};
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pci@1,2 { /* AES */
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};
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pci@f,0 {
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/config/("southbridge/amd/cs5536/dts");
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/* Interrupt enables for LPC bus.
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* Each bit is an IRQ 0-15. */
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lpc_serirq_enable = "0x000010da";
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/* LPC IRQ polarity. Each bit is an IRQ 0-15. */
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lpc_serirq_polarity = "0x0000EF25";
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/* 0:continuous 1:quiet */
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lpc_serirq_mode = "1";
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/* GPIO(0-0x20) for INT D:C:B:A, 0xFF=none.
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* See virtual PIC spec. */
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enable_gpio_int_route = "0x0D0C0700";
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enable_USBP4_device = "1";
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};
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pci@f,2 {
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/config/("southbridge/amd/cs5536/ide");
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};
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ioport@2e {
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/config/("superio/winbond/w83627hf/dts");
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com1enable = "1";
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};
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};
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};
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