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https://github.com/fail0verflow/switch-coreboot.git
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29dd0b58e3
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://coreboot.org/repository/coreboot-v3@634 f3766cd6-281f-0410-b1cd-43a5c92072e9
81 lines
2.8 KiB
C
81 lines
2.8 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007 Ronald G. Minnich <rminnich@gmail.com>
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* Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <cpu.h>
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#include <console.h>
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/**
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* Print an error message which says why the RAM initialization failed,
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* then halt the processor(s).
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*
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* @param why The reason why the RAM initialization failed.
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*/
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void ram_failure(const char *why)
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{
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printk(BIOS_EMERG, "RAM failure: %s: Halting\n", why);
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hlt();
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}
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/* Northbridge or memory controller code must define these functions. */
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void ram_set_registers(void *ctrl, int i);
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int ram_set_spd_registers(void *ctrl, int i);
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void ram_enable(int controllers, void *ctrl);
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/**
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* ram_initialize() is is the main RAM init function.
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*
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* It sets basic registers that can not be detected, then does the SPD step.
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* Mainboards and other code can skip one of these steps by the expedient
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* of making it an empty function.
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*
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* @param controllers How many memory controllers there are.
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* @param ctrl Pointer to the mem control structure. This is a generic pointer,
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* since the structure is wholly chip-dependent, and a survey of
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* all the types makes it clear that a common struct is not
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* possible. We can not use the device tree here as this code is
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* run before the device tree is available.
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*/
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void ram_initialize(int controllers, void *ctrl)
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{
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int i;
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/* Set the registers we can set once to reasonable values. */
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for (i = 0; i < controllers; i++) {
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printk(BIOS_INFO,
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"Setting registers of RAM controller %d\n", i);
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ram_set_registers(ctrl, i);
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}
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/* Now setup those things we can auto-detect via SPD. */
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for (i = 0; i < controllers; i++) {
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printk(BIOS_INFO,
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"Setting SPD based registers of RAM controller %d\n", i);
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ram_set_spd_registers(ctrl, i);
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}
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/* Now that everything is setup enable the RAM. Some chipsets do
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* the work for us while on others we need to it by hand.
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*/
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printk(BIOS_DEBUG, "Enabling RAM\n");
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ram_enable(controllers, ctrl);
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/* RAM initialization is done. */
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printk(BIOS_DEBUG, "RAM enabled successfully\n");
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}
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