mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
6220b632e7
- I left LB_TAG_ intact because they are used by the payloads - file renames are still missing. see next commit - some lb_ renames might be missing. feel free to provide patches. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://coreboot.org/repository/coreboot-v3@564 f3766cd6-281f-0410-b1cd-43a5c92072e9
46 lines
2 KiB
Text
46 lines
2 KiB
Text
#FIG 3.2
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Landscape
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Center
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Inches
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Letter
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100.00
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Single
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-2
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1200 2
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2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
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2400 6225 6900 6225
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2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
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2400 6975 6900 6975
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2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5
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4650 6975 6900 6975 6900 6675 4650 6675 4650 6975
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2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5
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4650 6225 6900 6225 6900 5775 4650 5775 4650 6225
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2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
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2400 4050 6900 4050
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2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5
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2400 450 6900 450 6900 7350 2400 7350 2400 450
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2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
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2400 4800 6900 4800
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4 0 0 50 -1 0 12 0.0000 4 135 750 2550 7275 JMP start\001
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4 0 0 50 -1 0 12 0.0000 4 135 375 4350 6450 VPD\001
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4 0 0 50 -1 0 12 0.0000 4 180 1935 4800 6900 VPD checksum (4 bytes)\001
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4 0 0 50 -1 0 12 0.0000 4 180 1980 4800 6075 Code Checksum (4 bytes)\001
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4 0 0 50 -1 0 12 0.0000 4 135 690 1500 7350 0xfffffff0\001
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4 0 0 50 -1 0 12 0.0000 4 135 720 1500 6375 0xffffff00\001
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4 0 0 50 -1 0 12 0.0000 4 135 960 3375 675 LAR archive\001
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4 0 0 50 -1 0 12 0.0000 4 135 360 3375 900 lzma\001
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4 0 0 50 -1 0 12 0.0000 4 135 420 3375 1125 nrv2b\001
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4 0 0 50 -1 0 12 0.0000 4 135 1080 3375 1350 normal/initram\001
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4 0 0 50 -1 0 12 0.0000 4 135 1635 3375 1575 normal/coreboot.lzma\001
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4 0 0 50 -1 0 12 0.0000 4 135 1170 3375 1800 fallback/initram\001
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4 0 0 50 -1 0 12 0.0000 4 135 1725 3375 2025 fallback/coreboot.lzma\001
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4 0 0 50 -1 0 12 0.0000 4 135 2130 3375 2250 memtest86/memtest86.lzma\001
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4 0 0 50 -1 0 12 0.0000 4 180 990 3375 2475 vgabios.lzma\001
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4 0 0 50 -1 0 12 0.0000 4 180 1020 2625 4275 Basic startup\001
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4 0 0 50 -1 0 12 0.0000 4 180 1365 4425 4425 src/cpu/x86/crt0.S\001
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4 0 0 50 -1 0 12 0.0000 4 135 1320 3150 5025 Device Tree Blob\001
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4 0 0 50 -1 0 12 0.0000 4 135 1365 3150 5250 Device Tree Code\001
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4 0 0 50 -1 0 12 0.0000 4 180 1440 3150 5475 CPIO code support\001
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4 0 0 50 -1 0 12 0.0000 4 180 2610 3150 5700 FLASH recovery from serial ROM\001
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4 0 0 50 -1 0 12 0.0000 4 135 375 2925 4500 CAR\001
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4 0 0 50 -1 0 12 0.0000 4 180 1845 2925 4650 Pre-initram device setup\001
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