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https://github.com/fail0verflow/switch-coreboot.git
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6220b632e7
- I left LB_TAG_ intact because they are used by the payloads - file renames are still missing. see next commit - some lb_ renames might be missing. feel free to provide patches. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://coreboot.org/repository/coreboot-v3@564 f3766cd6-281f-0410-b1cd-43a5c92072e9
43 lines
1.3 KiB
C
43 lines
1.3 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007 coresystems GmbH
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* (Written by Stefan Reinauer <stepan@coresystems.de> for coresystems GmbH)
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* Copyright (C) 2007 Ronald G. Minnich <rminnich@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
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*/
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#include <io.h>
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#include <uart8250.h>
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/**
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* UART init.
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*/
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void uart_init(void)
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{
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unsigned ttysx_div;
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#if 0
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unsigned ttysx_index;
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static const unsigned char divisor[] = { 1, 2, 3, 6, 12, 24, 48, 96 };
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// read CMOS settings?
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ttysx_index = read_option(CMOS_VSTART_baud_rate, CMOS_VLEN_baud_rate, 0);
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ttysx_index &= 7;
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ttysx_div = divisor[ttysx_index];
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#else
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ttysx_div = TTYSx_DIV;
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#endif
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uart8250_init(TTYSx_BASE, ttysx_div, UART_LCS);
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}
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