mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
This is a potentially good pointer to where someone can take this. While startup was working, BSP now explodes once the AP stops, while BSP is doing startup IPI loop send #2. The code needs to be hardened; I think use of the shared variables would really make it much more solid. This would be a good undergrad student project if someone is looking for one. Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://coreboot.org/repository/coreboot-v3@1145 f3766cd6-281f-0410-b1cd-43a5c92072e9
139 lines
3.4 KiB
ArmAsm
139 lines
3.4 KiB
ArmAsm
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2002 Linux Networx
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* (Written by Eric Biederman <ebiederman@lnxi.com> for Linux Networx)
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* Copyright (C) 2004 Ollie Lo
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* Copyright (C) 2005 YingHai Lu
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* Copyright (C) Copyright (C) 2005-2007 Stefan Reinauer <stepan@openbios.org>
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* Copyright (C) 2009 Ronald G. Minnich <rminnich@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
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*/
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/* POST_ZERO writes a POST_CODE at zero. Note that once we load %ds from %cs, "0" is at the start of this function!
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* This is debug only; you can't use it on systems with more than one core. It should be left off by default.
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*/
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#define NO_POST_ZERO
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#ifdef NO_POST_ZERO
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#define POST_ZERO(x)
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#else
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#define POST_ZERO(x) movw x, 0
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#endif
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.text
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.globl _secondary_start, _secondary_start_end
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_secondary_start:
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1:
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.code16
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.balign 4096
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cli
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POST_ZERO($0xdead)
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xorl %eax, %eax
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movl %eax, %cr3 /* Invalidate TLB*/
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/* On hyper threaded cpus, invalidating the cache here is
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* very very bad. Don't.
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*/
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POST_ZERO($0)
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movl $1b, %ebx
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POST_ZERO($1)
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POST_ZERO($2)
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/* setup the data segment */
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movw %cs, %ax
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movw %ax, 2
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POST_ZERO($3)
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movw %ax, %ds
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POST_ZERO($4)
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/* past this point, "0" means ds:0, i.e. cs:0, or the
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* segment part of the address.
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*/
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data32 lgdt gdtaddr - _secondary_start
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// data32 lgdt %cs:gdtptr
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POST_ZERO($5)
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movl %cr0, %eax
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POST_ZERO($6)
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andl $0x7FFAFFD1, %eax /* PG,AM,WP,NE,TS,EM,MP = 0 */
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POST_ZERO($7)
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orl $0x60000001, %eax /* CD, NW, PE = 1 */
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POST_ZERO($8)
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movl %eax, %cr0
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POST_ZERO($9)
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/* This jump pops us into 32-bit protected mode */
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data32 ljmp $0x8, $secondary32
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POST_ZERO($0xa)
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1:
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.code32
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secondary32:
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POST_ZERO($0x11)
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movw $0x10, %ax
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movw %ax, %ds
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/* having a post here for testing is useful.
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*If ds is bad for some reason, we'll reboot */
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POST_ZERO($0x13)
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movw %ax, %es
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movw %ax, %ss
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movw %ax, %fs
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movw %ax, %gs
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POST_ZERO($0x17)
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/* Load the Interrupt descriptor table */
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lidt idtarg
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/* Set the stack pointer */
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movl -4(%ebx),%esp
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movl $0, -4(%ebx)
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/* tested to this point but not past it */
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/* AP sees the stack value set to 0 */
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call secondary_cpu_init
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1: hlt
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jmp 1b
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.align 4
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gdt_limit = gdt_end - gdt - 1 /* Compute the table limit. */
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gdt:
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gdtptr:
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.word gdt_end - gdt -1 /* Compute the table limit. */
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.long gdt /* We know the offset. */
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.word 0
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/* selgdt 0x08, flat code segment */
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.word 0xffff, 0x0000
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.byte 0x00, 0x9b, 0xcf, 0x00
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/* selgdt 0x10, flat data segment */
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.word 0xffff, 0x0000
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.byte 0x00, 0x93, 0xcf, 0x00
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gdt_end:
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gdtaddr:
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.word gdt_limit /* the table limit */
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.long gdt /* we know the offset */
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idtarg:
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.word _idt_end - _idt - 1 /* limit */
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.long _idt
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.word 0
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_idt:
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.fill 20, 8, 0 # idt is unitiailzed
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_idt_end:
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_secondary_start_end:
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.code32
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