mirror of
https://github.com/fail0verflow/switch-coreboot.git
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5f27d204bc
adaption of the v2 code, with significant cleanup and simplification. It also works in CAR mode, and has no .bss or .data usage. It provides for a way to provide AP POST codes to the BSP. Since one common file with amd changed (lapic.h) I have build-tested this against serengeti and it is fine. It builds and I'll be testing it as soon as I can find the power supply for the kontron (it got "borrowed"). Index: arch/x86/intel/core2/init_cpus.c new file. Basically an adaptation of the v2 code to v3. All global variables removed. One big change to note: there is a stack struct, and the parameters to the secondary_start are struct members. Thus the BSP can watch the AP, and, neater, the AP can POST to a shared variable and the BSP can see how far it got. Index: arch/x86/secondary.S .S startup for AP. Index: arch/x86/Kconfig Delete a dependency. Index: northbridge/intel/i945/reset_test.c Add real cold boot detection. Index: mainboard/kontron/986lcd-m/Makefile Add some new build files. Index: mainboard/kontron/986lcd-m/stage1.c Get rid of ' in #warning that confused some tool. Index: mainboard/kontron/986lcd-m/initram.c Call init_cpus. Index: mainboard/kontron/Kconfig Turn off SMM for now. Index: include/arch/x86/lapic.h Correct a static inline declaration. Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://coreboot.org/repository/coreboot-v3@1136 f3766cd6-281f-0410-b1cd-43a5c92072e9
258 lines
6.5 KiB
Text
258 lines
6.5 KiB
Text
##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2006-2007 coresystems GmbH
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## (Written by Stefan Reinauer <stepan@coresystems.de> for coresystems GmbH)
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; either version 2 of the License, or
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## (at your option) any later version.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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config ARCH_X86
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boolean
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help
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This option is used to set the architecture of a mainboard.
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It is usually set in mainboard/*/Kconfig.
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config ARCH
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string
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default x86
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depends ARCH_X86
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help
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This is the name of the respective subdirectory in arch/.
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config CPU_I586
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boolean
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help
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CPU type. At the moment this option selects the reset vector and
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Cache-as-RAM (CAR) implementation for a mainboard. See
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arch/x86/Makefile for more hints on possible values.
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It is usually set in mainboard/*/Kconfig.
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config CPU_AMD_GEODELX
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boolean
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help
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CPU type. At the moment this option selects the reset vector and
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Cache-as-RAM (CAR) implementation for a mainboard. See
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arch/x86/Makefile for more hints on possible values.
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It is usually set in mainboard/*/Kconfig.
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config CPU_AMD_K8
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boolean
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help
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CPU type. At the moment this option selects the reset vector and
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Cache-as-RAM (CAR) implementation for a mainboard. See
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arch/x86/Makefile for more hints on possible values.
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It is usually set in mainboard/*/Kconfig.
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config CPU_INTEL_CORE2
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boolean
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help
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CPU type. At the moment this option selects the reset vector and
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Cache-as-RAM (CAR) implementation for a mainboard. See
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arch/x86/Makefile for more hints on possible values.
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It is usually set in mainboard/*/Kconfig.
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config CPU_VIA_C7
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boolean
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help
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CPU type. At the moment this option selects the reset vector and
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Cache-as-RAM (CAR) implementation for a mainboard. See
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arch/x86/Makefile for more hints on possible values.
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It is usually set in mainboard/*/Kconfig.
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config HPET
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boolean
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depends CPU_AMD_K8
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help
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Whether to configure a High Precision Event Timer (HPET). Note that
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HPETs are known to be bug-prone.
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config SMM
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boolean
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help
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Whether to configure System Management Mode support.
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This is mainboard-enabled. This is a tricky option that
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should not be enabled/disabled casually, as some chipsets
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will not work without some form of SMM enabled.
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config K8_REV_F_SUPPORT
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hex
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default 0 if CPU_AMD_K8
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help
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Whether to include rev F support.
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config K8_SCAN_PCI_BUS
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hex
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default 0 if CPU_AMD_K8
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help
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Whether to scan the PCI bus in stage1.
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config K8_ALLOCATE_IO_RANGE
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hex
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default 0 if CPU_AMD_K8
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help
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Whether to allocate I/O space in stage1.
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config K8_ALLOCATE_MMIO_RANGE
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hex
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default 0 if CPU_AMD_K8
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help
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Whether to allocate MMIO space in stage1.
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Comment from code: Do we need allocate MMIO? Currently we direct
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last 64M to southbridge link (sblink) only. We can not lose access
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to last 4M range to ROM.
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config LOGICAL_CPUS
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hex
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default 1
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help
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How many logical CPUs there are. FIXME.
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config MAX_PHYSICAL_CPUS
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hex
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default 1
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help
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Maximum number of physical CPUs (sockets).
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config MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED
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hex
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default 0 if CPU_AMD_K8
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help
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Config with 4 CPUs even if more are installed.
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config CROSS_BAR_47_56
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hex
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default 0 if CPU_AMD_K8
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help
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Configure for the type of crossbar on the mainboard.
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config PIRQ_TABLE
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boolean
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help
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This option is used to determine whether the mainboard has
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a PIRQ table, which is the old way to set up interrupt routing.
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It is usually set in mainboard/*/Kconfig.
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config ACPI_TABLE
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boolean
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help
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This option is used to determine whether the mainboard has
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an ACPI table.
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It is usually set in mainboard/*/Kconfig.
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config SMP
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boolean
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depends CPU_I586 || CPU_AMD_K8
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default 0
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help
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This option is used to enable certain functions to make coreboot
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work correctly on symmetric multi processor systems.
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It is usually set in mainboard/*/Kconfig.
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config IOAPIC
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boolean
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depends ARCH_X86 && CPU_AMD_K8 || CPU_INTEL_CORE2
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default 0
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help
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If you want to configure an IOAPIC, set this.
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config CARBASE
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hex
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default 0x8f000 if CPU_I586
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default 0x80000 if CPU_AMD_GEODELX
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default 0xc8000 if CPU_AMD_K8
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default 0xffef0000 if CPU_VIA_C7
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default 0xffdf8000 if CPU_INTEL_CORE2
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help
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This option sets the base address of the area used for CAR.
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config CARSIZE
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hex
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default 0x1000 if CPU_I586
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default 0x8000 if CPU_AMD_GEODELX
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default 0x8000 if CPU_AMD_K8
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default 0x8000 if CPU_VIA_C7
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default 0x8000 if CPU_INTEL_CORE2
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help
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This option sets the size of the area used for CAR.
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config MTRR
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bool
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default n if CPU_AMD_GEODELX
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default y if CPU_AMD_K8
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default y if CPU_VIA_C7
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default y if CPU_INTEL_CORE2
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help
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This option indicates if a cpu has MTRR support.
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config CBMEMK
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hex
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default 0x1000 if CPU_I586
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default 0x1000 if CPU_AMD_GEODELX
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default 0x2000 if CPU_AMD_K8
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default 0x1000 if CPU_VIA_C7
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default 0x1000 if CPU_INTEL_CORE2
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help
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This option sets the top of the memory area, in KiB,
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used for coreboot.
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config K8_HT_FREQ_1G_SUPPORT
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hex
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default 1 if CPU_AMD_K8
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help
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1 GHz support. Opteron E0 or later can support 1G HT,
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but still depends on the mainboard.
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config HT_FREQ_800MHZ
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hex
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default 1 if CPU_AMD_K8
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help
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Can we run HT at 800 MHz.
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config USBDEBUG_DIRECT
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boolean
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depends SOUTHBRIDGE_NVIDIA_MCP55
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default 0
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help
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Determines if we enable USB Direct debugging. If you don't have
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a dongle, this is probably of no value to you.
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config APIC_ID_OFFSET
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hex "APIC ID offset"
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default 0x10
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depends IOAPIC
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help
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This is entirely mainboard dependent. 0x10 is a *typical* setting
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but not always a good setting.
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menu "Debugging"
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config CARTEST
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bool "Test CAR area"
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default n
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help
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Test the CAR area after it has been set up.
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config CHECK_STACK_USAGE
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bool "Check stack usage"
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default n
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help
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Continuously monitor stack usage and keep statistics.
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The monitoring code is invoked from printk because printk is
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a leaf function and consumes quite a bit of stack for itself.
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This slows down booting a LOT.
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endmenu
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