Add a Makefile.inc, based on sconfig's, to use the _shipped variants
so that the build doesn't have to generate them with flex & bison.
The GENPARSER check is inactive, and will be updated in the next
commit.
Add the c_shipped & h_shipped files for the current .l & .y files.
BUG=none
BRANCH=none
TEST=none
Change-Id: Id5065158c990b06a03d4e7ef55244248879b57a6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: cfce793052
Original-Change-Id: Ia6c68bfb6e0611ceb6bc76cc66e43266bafc98ad
Original-Signed-off-by: Martin Roth <martinroth@google.com>
Original-Reviewed-on: https://review.coreboot.org/19228
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/480282
Use linker instead of '#include *.c'.
The smbus_fixup() was changed not to use a structure that's defined by a
northbridge since multiple different northbridges can be used. Instead
the caller now directly passed the memory slot details.
BUG=none
BRANCH=none
TEST=none
Change-Id: I247296dd5c3bd6fe59a74280a98a7d4fcf09d991
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b0161fd2d8
Original-Change-Id: Ia369ece6365accbc531736fc463c713bbc134807
Original-Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Original-Reviewed-on: https://review.coreboot.org/19082
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/480281
Includes the DRAM controller device that knows which where the division
between addresses routed to the main memory and to the PCI bus is.
BUG=none
BRANCH=none
TEST=none
Change-Id: I9246a4b6ddeec914efe99c2df7b13eeb5166577d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 38d1eb4403
Original-Change-Id: Id4cfeb8ff32de37723eee68a61c576e657dad30b
Original-Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Original-Reviewed-on: https://review.coreboot.org/18896
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/480280
This is the actual PCI Id of the internal graphics.
BUG=none
BRANCH=none
TEST=none
Change-Id: I4b703e94434fc2a6fb13a17dff29f030dc4933c4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 43156f6625
Original-Change-Id: I2a25ed35a5b01de6da905619fa9fce96738d1c0e
Original-Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Original-Reviewed-on: https://review.coreboot.org/18895
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://chromium-review.googlesource.com/480279
Without them the BS_DEV_RESOURCES stage won't traverse the bridge and
the graphics controller would be left without resources assigned.
Even worse, the resources would stay based in offset 0 which confuses
the MTRR setting code and causes a good chunk of the DRAM to be set
to type write combining.
With the patch applied, the resources are set:
Show resources in subtree (Root Device)...After assigning values.
...
PCI: 00:01.0 child on link 0 PCI: 01:00.0
+ PCI: 00:01.0 resource base ffff size 0 align 0 gran 0 limit ffff flags 60080100 index 0
+ PCI: 00:01.0 resource base f8000000 size 4000000 align 26 gran 0 limit fbffffff flags 60081200 index 1
+ PCI: 00:01.0 resource base fc000000 size 1010000 align 24 gran 0 limit fd00ffff flags 60080200 index 2
PCI: 01:00.0
- PCI: 01:00.0 resource base 0 size 4000000 align 26 gran 26 limit ffffffff flags 1200 index 10
- PCI: 01:00.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffff flags 200 index 14
- PCI: 01:00.0 resource base 0 size 10000 align 16 gran 16 limit ffffffff flags 2200 index 30
+ PCI: 01:00.0 resource base f8000000 size 4000000 align 26 gran 26 limit fbffffff flags 60001200 index 10
+ PCI: 01:00.0 resource base fc000000 size 1000000 align 24 gran 24 limit fcffffff flags 60000200 index 14
+ PCI: 01:00.0 resource base fd000000 size 10000 align 16 gran 16 limit fd00ffff flags 60002200 index 30
And the caching mode is set properly:
MTRR: Physical address space:
-0x0000000000000000 - 0x0000000004000000 size 0x04000000 type 1
-0x0000000004000000 - 0x000000000e000000 size 0x0a000000 type 6
-0x000000000e000000 - 0x0000000100000000 size 0xf2000000 type 0
+0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
+0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
+0x00000000000c0000 - 0x000000000e000000 size 0x0df40000 type 6
+0x000000000e000000 - 0x00000000f8000000 size 0xea000000 type 0
+0x00000000f8000000 - 0x00000000fc000000 size 0x04000000 type 1
+0x00000000fc000000 - 0x0000000100000000 size 0x04000000 type 0
The problem was also spot and discussed here:
http://coreboot.coreboot.narkive.com/E9eGauzH/via-c7-on-bcom-winnet-p680-l1-l2-cache-very-slow
BUG=none
BRANCH=none
TEST=none
Change-Id: I5368a607d44f0f0afae0a3d1ecc424f0fa8cb9bd
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2523dd031c
Original-Change-Id: Idb4979b206838dd6455b2a16de14dc74f83af921
Original-Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Original-Reviewed-on: https://review.coreboot.org/18894
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/480278
Otherwise, it locks up quickly. Not sure which ones are actually needed
and why, couldn't bisect it into removing even a single one.
The factory BIOS on a Neoware G170 does 200 0xed reads between setting
the registers too.
BUG=none
BRANCH=none
TEST=none
Change-Id: I11e149bad93bc05eb6e7ef8373ad4ae834d02633
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b31a066e0d
Original-Change-Id: I6aa38768d84dd42c9c720c917a99e6b4b1e03427
Original-Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Original-Reviewed-on: https://review.coreboot.org/18893
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/480110
Enable SERIRQ in quiet or continuous mode based on Kconfig.
Defaults to quite mode.
BUG=none
BRANCH=none
TEST=none
Change-Id: I1f479d87f10a1fdac21b71de106e07673d89c92b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3eec9dda1f
Original-Change-Id: Ib40a84719fcc3a5d6b3000c3c0412f1bcf629609
Original-Signed-off-by: Marc Jones <marcj303@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19234
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/480109
Clean up hudson PM register accesses with some register defines.
BUG=none
BRANCH=none
TEST=none
Change-Id: Id36b89e35d22fe4c878a9d9dc5abf5d76633ab1a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d771786058
Original-Change-Id: I5ccf27a2463350baec53b7c79fe0fd4ec6c31306
Original-Signed-off-by: Marc Jones <marcj303@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19233
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/480108
On some architectures (like AArch64), /dev/mem mappings outside of the
area marked as normal RAM use a memory type that does not support
unaligned accesses. The libc memcpy() implementation on these
architectures may not know or expect that and make an unaligned access
for certain source/dest/length alignments. Add a custom memcpy()
implementation that takes these restrictions into account and use it
anywhere we copy straight out of /dev/mem memory.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ia5b395d84a3279913432045d97a32eabaad8da8f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 127a79e0b6
Original-Change-Id: I03eece380a14a69d4be3805ed72fba640f6f7d9c
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18300
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/480107
Update from commit 124af94f - Fri Feb 26, 2016
(skylake boards: unconditionally re-enable 8254 PIT for legacy)
To commit eb583fa8 - Wed Mar 29, 2017
(rk3399_sdhci: Reintroduce PHY power-cycling at 52MHz)
This brings the stable version of depthcharge forward by 325 commits.
BUG=none
BRANCH=none
TEST=none
Change-Id: I47dcabd8e8ca63d6fba94f93bfeae93d1bde722a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 973104ba1f
Original-Change-Id: I31b3235df6d36409ff1b365e6adb6852281df097
Original-Signed-off-by: Martin Roth <martinroth@google.com>
Original-Reviewed-on: https://review.coreboot.org/19220
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/480106
Update from commit 2afd66eb - Fri Jul 29, 2016
([pixbuf] Enable PNG format by default)
To commit fd6d1f46 - Fri Mar 31, 2017
([thunderx] Use ThunderxConfigProtocol to obtain board configuration)
This moves the stable iPXE commit forward 144 commits.
BUG=none
BRANCH=none
TEST=none
Change-Id: I6d4fd8e38d5adfcd4223c14f666d8963af21a7cc
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1a693958eb
Original-Change-Id: Ia0c97f863be39632c9206ca95b3857047fc37e26
Original-Signed-off-by: Martin Roth <martinroth@google.com>
Original-Reviewed-on: https://review.coreboot.org/19221
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Timothy Pearson <tpearson@raptorengineering.com>
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/480105
Vendor BIOS leaves UPMC1 untouched (on 945gc the default is 0x0203).
Not running PCIEx16 init which is valid for 945gm seems to fix all
issues and instabilities related to the PEG port.
According to lspci the link width is at the desired x16.
It is unknown if devices requesting a lower width work automatically
or need more configuration.
What happens is that IGD gets disabled by the disable function in
gma.c when an external GPU is found unless
CONFIG_ONBOARD_VGA_IS_PRIMARY is set.
Setting IGD as secondary makes Linux (4.10) hang, so this behavior is
a requirement for now.
TESTED on P5GC-MX with a discrete GPU and both
CONFIG_ONBOARD_VGA_IS_PRIMARY set and unset.
BUG=none
BRANCH=none
TEST=none
Change-Id: I305d73ec4472f7df1618d5da29853ffcfb048e30
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2f6b52e3a0
Original-Change-Id: I6da8aa7714073f4b34df5ae3c1eb4c19e27ddc97
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/18549
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/480104
Remove the ACPI ALS device from the EC configuration because this system
has an ALS that is presented through the new EC sensor interface rather
than the legacy ACPI interface.
BUG=b:37179776
BRANCH=none
TEST=Boot an Eve device and ensure that 'acpi-als' device is not present
in /sys/bus/iio/devices.
Change-Id: Idd98d9faf54db5fea2265ed54c358d284d45c03d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f13e250152
Original-Change-Id: Ie18b8a661e4d16464784ca8a227586036e7631de
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19265
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/480103
Set UART0 to "PchSerialIoSkipInit" so the pins for this device are not
set back to native mode by FSP when configured as GPIO input by coreboot.
Now that FSP is not touching the pins I also removed the workaround to
reconfigure the pins after FSP.
BUG=b:35647877
BRANCH=none
TEST=Verify that GPP_C8-GPP_C11 are configured as GPIO input once the OS
is booted and they are not set back to native function by FSP.
Change-Id: I688433e8b6556c5f3e2c374481cd29d8351c0032
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e49b866c7c
Original-Change-Id: Ifec4fa3e66ceeb660bad00c66bc7bd44bb457a01
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19264
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/480102
These lines act as inputs to both EC and AP and when the corresponding
TCPC mux is in low power mode the line is floating. Add an internal
pull-down to each GPIO to prevent it from floating in this state.
BUG=b:35775012
BRANCH=none
TEST=Verify that the kernel does not see a device present on DP when
the TCPC mux is in low power mode.
Change-Id: I6d940004364e4a5cc338ff2063d034d12c1dcf88
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 30783d84cf
Original-Change-Id: Ie229f84871e9994467c0ab660cc7e271a51d9cbb
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19263
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/480101
With EuP and PME enabled the USB power turns off during S5.
BUG=none
BRANCH=none
TEST=none
Change-Id: I57d70a85586832384e5c6fc9d65a681404b7a48a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5ad939679f
Original-Change-Id: I8b9fd7bb308f544401f90f8aa5ffaec61251b2b3
Original-Signed-off-by: Nicola Corna <nicola@corna.info>
Original-Reviewed-on: https://review.coreboot.org/19073
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://chromium-review.googlesource.com/480100
In order to support a standard "docked" config disable Deep S3 when
connected to AC power. This allows USB devices to wake the device
from suspend if it is externally powered, but still retains the
lower power state when running on battery.
BUG=b:36723679
BRANCH=none
TEST=manual testing on Eve for USB wake behavior:
1) when suspended on battery USB keyboard does not wake
2) when suspended while connected to AC a USB keyboard does wake
3) if suspended with AC, and then AC is removed, system does not
wake with USB keyboard
4) if suspended without AC, and then AC is added, system does not
wake with USB keyboard (it cannot get enabled without waking and
re-suspending)
Change-Id: I522b50c16fa0c4c3ba3731075fe29d3e799935d4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 73ff0fbd2e
Original-Change-Id: I670e39d42cdb5b80612206da899be82ef3b2cbf2
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19240
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/480098
Enable the Intel WiFi SAR feature for Eve, which will be used to
provide wifi power tables based on values read from VPD.
This is enabled based on CONFIG_CHROMEOS because it relies on the
presence of VPD code from vendorcode/google/chromeos.
BUG=b:36727652
BRANCH=none
TEST=test on Eve by setting "wifi_sar" in VPD and ensuring that
the ACPI WIFI device gets the expected "WRDS" and "EWRD" tables
with the values that were set in VPD.
Change-Id: I124395715f3b074c74ce8b9436b561143aceac46
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 654c8de9f1
Original-Change-Id: I11c129baca891221177575108ac09ba1707b516e
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19241
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/480097
Currently when enabling Deep S3 or Deep S5 it unconditionally gets enabled
in both DC and AC states. However since using Deep S3 disables some
expected features like wake-on-USB it is not always desired to enable the
same state in both modes.
To address this split the setting and add a separate config for Deep Sx in
AC and DC states.
All motherboards that set this config were updated, but there is no actual
change in behavior in this commit.
BUG=b:36723679
BRANCH=none
TEST=This commit has no runtime visible changes, I verified on Eve that the
Deep SX config registers are unchanged, and it compiles for all affected boards.
Change-Id: Ifceb6039323c6a755ea4a0c26356aa778e2d04d1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1fe32d6bb2
Original-Change-Id: I590f145847785b5a7687f235304e988888fcea8a
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19239
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/480096
These lines act as inputs to both EC and AP. Thus, add internal
pull-downs to prevent them from floating.
BUG=b:35648530
Change-Id: Ia73ecfe432c5543d37d5ff166124d364006138ae
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: bcbba801b8
Original-Change-Id: I42326c810775d5449e99e52e81870970247ce335
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19243
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/480095
Put all configs required for enabling cr50 SPI TPM on poppy under
POPPY_USE_SPI_TPM so that it can be enabled any time for testing SPI
TPM on this board.
Also, add required callback for irq status and devicetree config for
GSPI0.
BUG=b:36873582
Change-Id: Ie467753b802ccce1d50c5a982da77872ac274f30
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 82010835bf
Original-Change-Id: I67793093c006c1325fc16f669a96126525f83243
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19238
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/480094
1. Move common TIS macros to include/tpm.h.
2. Use common TIS macros while referring to status and access registers.
3. Add a new function claim_locality to properly check for required
access bits and claim locality 0.
BUG=b:36873582
Change-Id: I64501d5d78b82744e85433f34d0f94f82b45b370
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 260b297a89
Original-Change-Id: I11bf3e8b6e1f50b7868c9fe4394a858488367287
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19213
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/480093
CBGFX currently doesn't support portrait screens at all. This will have
to be fixed eventually but might take a bit of effort. As a first step
to make devices with a portrait panel somewhat usable, this patch will
just force a square canvas on these panels and keep the bottom part of
the screen black.
Also switch set_pixel to calculate framebuffer position via
bytes_per_line instead of x_resolution. This is supposed to be the
canonical way to do that and may differ in cases where the display
controller requires a certain alignment from framebuffer lines.
BRANCH=none
BUG=b:35774871
TEST=Boot Rowan in developer mode and see output on the
panel; below the developer screen square is completely black
Change-Id: I5e5423e5fe166b1fea54ab16f7e0dd31fcce00d7
Original-Change-Id: I47dd3bf95ab8a7d8b7e1913e0ddab346eedd46f1
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/479613
Commit-Ready: Daniel Kurtz <djkurtz@chromium.org>
Tested-by: Daniel Kurtz <djkurtz@chromium.org>
With recent change to use common block PCR (ccd8700c),
IOSF_BASE_ADDRESS was renamed to PCR_BASE_ADDRESS. However, SD card
change (99ce8a9b) was not rebased on top of it, so IOSF_BASE_ADDRESS
slipped into the tree. Fix this by replacing all occurrences of
IOSF_BASE_ADDRESS by PCR_BASE_ADDRESS.
CQ-DEPEND=CL:477153
BUG=None
BRANCH=reef
TEST=Compiles successfully for reef.
Change-Id: I40eb07be306035c940fc960896e0807d6c73bafa
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19277
Tested-by: build bot (Jenkins)
Reviewed-by: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/477410
Reviewed-by: Martin Roth <martinroth@chromium.org>
Currently sdcard CD host ownership is always owned by the GPIO driver.
Due to this sdcard detection fails during initial boot process and OS
fails to boot from sdcard.
This implements change in host ownership from acpi to GPIO driver when
kernel starts booting.
CQ-DEPEND=CL:477410
BUG=b:35648535
BRANCH=reef
TEST=Check OS boot from sdcard.
Change-Id: I042a8762dc1f9cb73e6a24c1e7169c9746b2ee14
Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Reviewed-on: https://review.coreboot.org/18947
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/477153
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Benson Leung <bleung@chromium.org>
The original document was written and committed with no regard to line
lengths. This makes it easier to write. Now it needs to be easier to
read, so wrap the lines at 80 characters where possible.
- A couple of headings had to be rewritten to keep them under 80
characters. This required the addition of a new paragraph that had
the old header.
- Remove URL text that was just duplicating the URL.
- All other text is the same, just wrapped.
BUG=none
BRANCH=none
TEST=none
Change-Id: I6c450c36dea4ae5eb6bbaf7fdb46d6b57d475137
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ccfea16cd4
Original-Change-Id: I44833c28750714fccb87296868c1ff78ab7f1d07
Original-Signed-off-by: Martin Roth <gaumless@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19076
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/475712
Using i2c_block_read speeds up reading SPD four to fivefold compared
to sequential byte read.
TESTED on Intel D945GCLF.
BUG=none
BRANCH=none
TEST=none
Change-Id: I28829a1ad5b834a9b32ba13815bdd55f78d96d13
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2a7c519c89
Original-Change-Id: I6d768a2ba128329168f26445a4fca6921c0c8642
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/18927
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/475711
Scarlet don't have eDP and MIPI driver is not ready, skipping
display for now or else Scarlet would be stuck in
reading eDP HPD because there even not power for it.
TEST=boot to kernel on Scarlet
Change-Id: Id2558eeb60900a25f2c99c42b338db2d9d80fd57
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4f4410dcbc
Original-Change-Id: I02ab4ef21bf77b98414f537aca57b46c11922348
Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
Original-Reviewed-on: https://review.coreboot.org/19237
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/474137
Due to issues with stability limit the SKU with K4EBE304EB-EGCF
memory to 1600MHz instead of 1866MHz.
BUG=b:37172778
BRANCH=none
TEST=pass stress testing on devices with this memory
Change-Id: I3dd16517ce8043d9a71e2da553f81861504a29ea
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 08117c412c
Original-Change-Id: I02af7e9c35e2c5b0b85223d58025cbd29841d973
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19227
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/474136
This is needed if one wants to use the header more than once.
BUG=none
BRANCH=none
TEST=none
Change-Id: If43ac3dafbb8e6b9052d6af9206d586d5a466ce1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f170e71630
Original-Change-Id: I375d08465b6c64cd91e7563e3917764507d779ba
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/19029
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/474135
Create Intel Common RTC code. This code currently only
contains the code for configuring RTC required in Bootblock phase
which has the following programming -
* Enable upper 128 bytes of CMOS.
BUG=none
BRANCH=none
TEST=none
Change-Id: I25d743418a00626e5fb199ce26c095acbf01902d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8e84723e02
Original-Change-Id: Id9dfcdbc300c25f43936d1efb5d6f9d81d3c8453
Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18558
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/474131
IOSF_SB message space is used to access registers mapped
on IOSF-SB. These registers include uncore CRs (configuration
registers) and chipset specific registers. The Private
Configuration Register (PCR) space is accessed on IOSF-SB
using destination ID also known as Port ID.
Access to IOSF-SB by the Host or System Agent is possible
over PSF via the Primary to Sideband Bridge (P2SB). P2SB will
forward properly formatted register access requests as CRRd and
CRWr request via IOSF-SB.
BUG=none
BRANCH=none
TEST=none
Change-Id: Id92e85334956d993168005f7737b623da039cbbb
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d579199f96
Original-Change-Id: I78526a86b6d10f226570c08050327557e0bb2c78
Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18669
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/474128
Update the I2C rise/fall timings based on newly measured values
on a new board with updated pull-up resistor values.
Touchscreen: rise time 98ns, fall time 38ms
Touchpad: rise time 111ns, fall time 41ns
TPM: rise time 112ns, fall time 34ns
BUG=b:35583133
BRANCH=none
TEST=Each I2C bus frequency was verified on a scope to be ~400MHz
Change-Id: Ib2b0598fb10c3e0e21161583362fc317d3e1f5c9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 92dde2fdd7
Original-Change-Id: Ibb3a15fa0cc862f36c1b9c63ac7847221020c4c0
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19202
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/474127
There is only one user for spi_get_config i.e. SPI ACPI. Also, the
values provided by spi_get_config are constant for now. Thus, get rid
of the spi_get_config call and fill in these constant values in SPI
ACPI code itself. If there is a need in the future to change these,
appropriate device-tree configs can be added.
BUG=b:36873582
Change-Id: Id2a1447d3112dc0f33f35b1357a039f1852da44d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5bda642bcb
Original-Change-Id: Ied38e2670784ee3317bb12e542666c224bd9e819
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19203
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/472721
When a platform is using postcar stage it's by definition not
tearing down cache-as-ram from within romstage prior to loading
ramstage. Because of this property there's no need to migrate
CAR_GLOBAL variables to cbmem.
BUG=none
BRANCH=none
TEST=none
Change-Id: I34c0ae5c9f5e862ad523c58ceeeb1ab3873bc4c3
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: bc17cdef0d
Original-Change-Id: I7c683e1937c3397cbbba15f0f5d4be9e624ac27f
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19215
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Tested-by: build bot (Jenkins)
Original-Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/472720
Bottom five LSBs are used to store the running frequency
of memory clock.
BUG=none
BRANCH=none
TEST=none
Change-Id: If241c224ecb5b5aed3e308d126cd1d7d0314417e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e522258907
Original-Change-Id: I2dfcf1950883836499ea2ca95f9eb72ccdfb979c
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19042
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/472718
